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? 2007 microchip technology inc. preliminary ds41236d pic12f508/509/16f505 data sheet 8/14-pin, 8-bit flash microcontrollers
ds41236d-page ii preliminary ? 2007 microchip technology inc. information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, micro id , mplab, pic, picmicro, picstart, pro mate, rfpic and smartshunt are registered trademarks of micr ochip technology incorporated in the u.s.a. and other countries. amplab, filterlab, linear active thermistor, migratable memory, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip tec hnology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, real ice, rflab, select mode, smart serial, smarttel, total endurance, uni/o, wiperlock and zena are tr ademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2007, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specifications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
? 2007 microchip technology inc. preliminary ds41236d-page 1 pic12f508/509/16f505 devices included in this data sheet: ?pic12f508 ?pic12f509 ?pic16f505 high-performance risc cpu: ? only 33 single-word instructions to learn ? all single-cycle instructions except for program branches, which are two-cycle ? 12-bit wide instructions ? 2-level deep hardware stack ? direct, indirect and relative addressing modes for data and instructions ? 8-bit wide data path ? 8 special function hardware registers ? operating speed: - dc ? 20 mhz clock input (pic16f505 only) - dc ? 200 ns instruction cycle (pic16f505 only) - dc ? 4 mhz clock input - dc ? 1000 ns instruction cycle special microcontroller features: ? 4 mhz precision internal oscillator: - factory calibrated to 1% ? in-circuit serial programming? (icsp?) ? in-circuit debugging (icd) support ? power-on reset (por) ? device reset timer (drt) ? watchdog timer (wdt) with dedicated on-chip rc oscillator for reliable operation ? programmable code protection ? multiplexed mclr input pin ? internal weak pull-ups on i/o pins ? power-saving sleep mode ? wake-wp from sleep on pin change ? selectable oscillator options: - intrc: 4 mhz precision internal oscillator - extrc: external low-cost rc oscillator - xt: standard crystal/resonator - hs: high-speed crystal/resonator (pic16f505 only) - lp: power-saving, low-frequency crystal - ec: high-speed external clock input (pic16f505 only) low-power features/cmos technology: ? operating current: - < 175 a @ 2v, 4 mhz, typical ? standby current: - 100 na @ 2v, typical ? low-power, high-speed flash technology: - 100,000 flash endurance - > 40 year retention ? fully static design ? wide operating voltage range: 2.0v to 5.5v ? wide temperature range: - industrial: -40 c to +85 c - extended: -40 c to +125 c peripheral features (pic12f508/509): ? 6 i/o pins: - 5 i/o pins with individual direction control - 1 input only pin - high current sink/source for direct led drive - wake-on-change - weak pull-ups ? 8-bit real-time clock/counter (tmr0) with 8-bit programmable prescaler peripheral features (pic16f505): ? 12 i/o pins: - 11 i/o pins with individual direction control - 1 input only pin - high current sink/source for direct led drive - wake-on-change - weak pull-ups ? 8-bit real-time clock/counter (tmr0) with 8-bit programmable prescaler 8/14-pin, 8-bit flas h microcontrollers
pic12f508/509/16f505 ds41236d-page 2 preliminary ? 2007 microchip technology inc. pin diagrams device program memory data memory i/o timers 8-bit flash (words) sram (bytes) pic12f508 512 25 6 1 pic12f509 1024 41 6 1 pic16f505 1024 72 12 1 pdip, soic, tssop v dd rb5/osc1/clkin rb4/osc2/clkout rb3/mclr /v pp 1 2 3 4 v ss rb0/icspdat 14 13 12 11 pic16f505 5 6 7 10 9 8 rc5/t0cki rc4 rc3 rb1/icspclk rb2 rc0 rc1 rc2 pdip, soic, msop v dd gp5/osc1/clkin gp4/osc2 gp3/mclr /v pp 1 2 3 4 v ss gp0/icspdat 8 7 6 5 pic12f508/509 gp1/icspclk gp2/t0cki dfn pic12f508/509 1 2 3 4 8 7 6 5 v ss gp0/icspdat gp1/icspclk gp2/t0cki v dd gp5/osc1/clkin gp4/osc2 gp3/mclr /v pp
? 2007 microchip technology inc. preliminary ds41236d-page 3 pic12f508/509/16f505 table of contents 1.0 general description......................................................................................................... ............................................................. 5 2.0 pic12f508/509/16f505 device varieties ...................................................................................... ............................................. 7 3.0 architectural overview ..................................................................................................... ........................................................... 9 4.0 memory organization ......................................................................................................... ........................................................ 15 5.0 i/o port .................................................................................................................... ................................................................... 29 6.0 timer0 module and tmr0 register ............................................................................................. .............................................. 33 7.0 special features of the cpu................................................................................................. ................................................... 39 8.0 instruction set summary ..................................................................................................... ....................................................... 55 9.0 development support......................................................................................................... ........................................................ 63 10.0 electrical characteristics ................................................................................................. ........................................................... 67 11.0 dc and ac characteristics graphs and charts ................................................................................ ......................................... 79 12.0 packaging information...................................................................................................... .......................................................... 87 index .......................................................................................................................... .......................................................................... 99 the microchip web site ......................................................................................................... ............................................................ 101 customer change notification service ........................................................................................... ................................................... 101 customer support............................................................................................................... ............................................................... 101 reader response ................................................................................................................ .............................................................. 102 product identification system .................................................................................................. .......................................................... 103 to our valued customers it is our intention to provide our valued customers with t he best documentation possible to ensure successful use of your microchip products. to this end, we will co ntinue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regard ing this publication, please contact the marketing communications department via e-mail at docerrors@mail.microchip.com or fax the reader response form in the back of this dat a sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? 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pic12f508/509/16f505 ds41236d-page 4 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds41236d-page 5 pic12f508/509/16f505 1.0 general description the pic12f508/509/16f505 devices from microchip technology are low-cost, high-performance, 8-bit, fully- static, flash-based cmos microcontrollers. they employ a risc architecture with only 33 single-word/ single-cycle instructions. all instructions are single cycle (200 s) except for program branches, which take two cycles. the pic12f508/509/16f505 devices deliver performance an order of magnitude higher than their competitors in the same price category. the 12-bit wide instructions are highly symmetrical, resulting in a typical 2:1 code compression over other 8-bit microcontrollers in its class. the easy-to-use and easy to remember instruction set reduces development time significantly. the pic12f508/509/16f505 products are equipped with special features that reduce system cost and power requirements. the power-on reset (por) and device reset timer (drt) eliminate the need for exter- nal reset circuitry. there are four oscillator configura- tions to choose from (six on the pic16f505), including intrc internal oscillator mode and the power-saving lp (low-power) oscillator mode. power-saving sleep mode, watchdog timer and code protection features improve system cost, power and reliability. the pic12f508/509/16f505 devices are available in the cost-effective flash programmable version, which is suitable for production in any volume. the customer can take full advantage of microchip?s price leadership in flash programmable microcontrollers, while benefiting from the flash programmable flexibility. the pic12f508/509/16f505 products are supported by a full-featured macro assembler, a software simula- tor, an in-circuit emulator, a ?c? compiler, a low-cost development programmer and a full featured program- mer. all the tools are supported on ibm ? pc and compatible machines. 1.1 applications the pic12f508/509/16f505 devices fit in applications ranging from personal care appliances and security systems to low-power remote transmitters/receivers. the flash technology makes customizing application programs (transmitter codes, appliance settings, receiver frequencies, etc.) extremely fast and conve- nient. the small footprint packages, for through hole or surface mounting, make these microcontrollers perfect for applications with space limitations. low cost, low power, high performance, ease-of-use and i/o flexibil- ity make the pic12f508/509/16f505 devices very ver- satile even in areas where no microcontroller use has been considered before (e.g., timer functions, logic and plds in larger systems and coprocessor applications). table 1-1: pic12f508/509/16f505 devices pic12f508 pic12f509 pic16f505 clock maximum frequency of operation (mhz) 4 4 20 memory flash program memory (words) 512 1024 1024 data memory (bytes) 25 41 72 peripherals timer module(s) tmr0 tmr0 tmr0 wake-up from sleep on pin change yes yes yes features i/o pins 5 5 11 input pins 1 1 1 internal pull-ups yes yes yes in-circuit serial programming yes yes yes number of instructions 33 33 33 packages 8-pin pdip, soic, msop, dfn 8-pin pdip, soic, msop, dfn 14-pin pdip, soic, tssop the pic12f508/509/16f505 devices have power-on reset, selectable watchdog timer, selectable code-protect, high i/o current capability and precision internal oscillator. the pic12f508/509/16f505 devices use serial programming with data pin rb0/gp0 and clock pin rb1/gp1.
pic12f508/509/16f505 ds41236d-page 6 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds41236d-page 7 pic12f508/509/16f505 2.0 pic12f508/509/16f505 device varieties a variety of packaging options are available. depend- ing on application and production requirements, the proper device option can be selected using the information in this section. when placing orders, please use the pic12f508/509/16f505 product identification system at the back of this data sheet to specify the correct part number. 2.1 quick turn programming (qtp) devices microchip offers a qtp programming service for factory production orders. this service is made available for users who choose not to program medium-to-high quantity units and whose code patterns have stabilized. the devices are identical to the flash devices but with all flash locations and fuse options already programmed by the factory. certain code and prototype verification procedures do apply before production shipments are available. please contact your local microchip technology sales office for more details. 2.2 serialized quick turn programming sm (sqtp sm ) devices microchip offers a unique programming service, where a few user-defined locations in each device are programmed with different serial numbers. the serial numbers may be random, pseudo-random or sequential. serial programming allows each device to have a unique number, which can serve as an entry code, password or id number.
pic12f508/509/16f505 ds41236d-page 8 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds41236d-page 9 pic12f508/509/16f505 3.0 architectural overview the high performance of the pic12f508/509/16f505 devices can be attributed to a number of architectural features commonly found in risc microprocessors. to begin with, the pic12f508/509/16f505 devices use a harvard architecture in which program and data are accessed on separate buses. this improves bandwidth over traditional von neumann architec- tures where program and data are fetched on the same bus. separating program and data memory fur- ther allows instructions to be sized differently than the 8-bit wide data word. instruction opcodes are 12 bits wide, making it possible to have all single-word instructions. a 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. a two-stage pipeline overlaps fetch and execution of instructions. consequently, all instructions (33) execute in a single cycle (200 ns @ 20 mhz, 1 s @ 4 mhz) except for program branches. table 3-1 below lists program memory (flash) and data memory (ram) for the pic12f508/509/16f505 devices. table 3-1: pic12f508/509/16f505 memory the pic12f508/509/16f505 devices can directly or indirectly address its register files and data memory. all special function registers (sfr), including the pc, are mapped in the data memory. the pic12f508/509/ 16f505 devices have a highly orthogonal (symmetri- cal) instruction set that makes it possible to carry out any operation, on any register, using any addressing mode. this symmetrical nature and lack of ?special optimal situations? make programming with the pic12f508/509/16f505 devices simple, yet efficient. in addition, the learning curve is reduced significantly. the pic12f508/509/16f505 devices contain an 8-bit alu and working register. the alu is a general purpose arithmetic unit. it performs arithmetic and boolean functions between data in the working register and any register file. the alu is 8 bits wide and capable of addition, subtrac- tion, shift and logical operations. unless otherwise mentioned, arithmetic operations are two?s comple- ment in nature. in two-operand instructions, one operand is typically the w (working) register. the other operand is either a file register or an immediate constant. in single operand instructions, the operand is either the w register or a file register. the w register is an 8-bit working register used for alu operations. it is not an addressable register. depending on the instruction executed, the alu may affect the values of the carry (c), digit carry (dc) and zero (z) bits in the status register. the c and dc bits operate as a borrow and digit borrow out bit, respec- tively, in subtraction. see the subwf and addwf instructions for examples. simplified block diagrams are shown in figure 3-1 and figure 3-2, with the corresponding pin described in table 3-2 and table 3-3. device memory program data pic12f508 512 x 12 25 x 8 pic12f509 1024 x 12 41 x 8 pic16f505 1024 x 12 72 x 8
pic12f508/509/16f505 ds41236d-page 10 preliminary ? 2007 microchip technology inc. figure 3-1: pic12f50 8/509 block diagram device reset timer power-on reset watchdog timer flash program memory 12 data bus 8 12 program bus instruction reg program counter ram file registers direct addr 5 ram addr 9 addr mux indirect addr fsr reg status reg mux alu w reg instruction decode and control timing generation osc1/clkin osc2 mclr v dd , v ss timer0 gpio 8 8 gp4/osc2 gp3/mclr /v pp gp2/t0cki gp1/iscpclk gp0/iscpdat 5-7 3 gp5/osc1/clkin stack 1 stack 2 512 x 12 or 25 x 8 or 1024 x 12 4 1 x 8 internal rc osc
? 2007 microchip technology inc. preliminary ds41236d-page 11 pic12f508/509/16f505 table 3-2: pic12f508/5 09 pinout description name function input type output type description gp0/icspdat gp0 ttl cmos bidirectional i/o pin. can be software programmed for internal weak pull-up and wake-up from sleep on pin change. icspdat st cmos in-circuit serial programming? data pin. gp1/icspclk gp1 ttl cmos bidirectional i/o pin. can be software programmed for internal weak pull-up and wake-up from sleep on pin change. icspclk st cmos in-circuit serial programming clock pin. gp2/t0cki gp2 ttl cmos bidirectional i/o pin. t0cki st ? clock input to tmr0. gp3/mclr /v pp gp3 ttl ? input pin. can be software programmed for internal weak pull-up and wake-up from sleep on pin change. mclr st ? master clear (reset). when configured as mclr , this pin is an active-low reset to the device. voltage on mclr /v pp must not exceed v dd during normal device operation or the device will enter programming mode. weak pull-up always on if configured as mclr . v pp hv ? programming voltage input. gp4/osc2 gp4 ttl cmos bidirectional i/o pin. osc2 ? xtal oscillator crystal output. connections to crystal or resonator in crystal oscillator mode (xt and lp modes only, gpio in other modes). gp5/osc1/clkin gp5 ttl cmos bidirectional i/o pin. osc1 xtal ? oscillator crystal input. clkin st ? external clock source input. v dd v dd ? p positive supply for logic and i/o pins. v ss v ss ? p ground reference for logic and i/o pins. legend: i = input, o = output, i/o = input/output, p = power, ? = not used, ttl = ttl input, st = schmitt trigger input, hv = high voltage
pic12f508/509/16f505 ds41236d-page 12 preliminary ? 2007 microchip technology inc. figure 3-2: pic16f 505 block diagram device reset timer power-on reset watchdog timer flash program memory 12 data bus 8 12 program bus instruction reg program counter ram file registers direct addr 5 ram addr 9 addr mux indirect addr fsr reg status reg mux alu w reg instruction decode and control timing generation osc1/clkin osc2/clkout mclr v dd , v ss timer0 portb 8 8 rb4/osc2/clkout rb3/mclr /v pp rb2 rb1/icspdat rb0/icspclk 5-7 3 rb5/osc1/clkin stack 1 stack 2 1k x 12 7 2 b y t e s internal rc osc portc rc4 rc3 rc2 rc1 rc0 rc5/t0cki
? 2007 microchip technology inc. preliminary ds41236d-page 13 pic12f508/509/16f505 table 3-3: pic16f505 pinout description name function input type output type description rb0/icspdat rb0 ttl cmos bidirectional i/o pin. can be software programmed for internal weak pull-up and wake-up from sleep on pin change. icspdat st cmos in-circuit serial programming? data pin. rb1/icspclk rb1 ttl cmos bidirectional i/o pin. can be software programmed for internal weak pull-up and wake-up from sleep on pin change. icspclk st cmos in-circuit serial programming clock pin. rb2 rb2 ttl cmos bidirectional i/o pin. rb3/mclr /v pp rb3 ttl ? input port. can be software programmed for internal weak pull-up and wake-up from sleep on pin change. mclr st ? master clear (reset). when configured as mclr , this pin is an active-low reset to the device. voltage on mclr /v pp must not exceed v dd during normal device operation or the device will enter programming mode. weak pull-up always on if configured as mclr . v pp hv ? programming voltage input. rb4/osc2/clkout rb4 ttl cmos bidirectional i/o pin. can be software programmed for internal weak pull-up and wake-up from sleep on pin change. osc2 ? xtal oscillator crystal output. connections to crystal or resonator in crystal oscillator mode (xt, hs and lp modes only). clkout ? cmos in extrc and intrc modes, the pin output can be configured for clkout, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. rb5/osc1/clkin rb5 ttl cmos bidirectional i/o pin. osc1 xtal ? crystal input. clkin st ? external clock source input. rc0 rc0 ttl cmos bidirectional i/o pin. rc1 rc1 ttl cmos bidirectional i/o pin. rc2 rc2 ttl cmos bidirectional i/o pin. rc3 rc3 ttl cmos bidirectional i/o pin. rc4 rc4 ttl cmos bidirectional i/o pin. rc5/t0cki rc5 ttl cmos bidirectional i/o pin. t0cki st ? clock input to tmr0. v dd v dd ? p positive supply for logic and i/o pins. v ss v ss ? p ground reference for logic and i/o pins. legend: i = input, o = output, i/o = input/output, p = power, ? = not used, ttl = ttl input, st = schmitt trigger input, hv = high voltage
pic12f508/509/16f505 ds41236d-page 14 preliminary ? 2007 microchip technology inc. 3.1 clocking scheme/instruction cycle the clock input (osc1/clkin pin) is internally divided by four to generate four non-overlapping quadrature clocks, namely q1, q2, q3 and q4. internally, the pc is incremented every q1 and the instruction is fetched from program memory and latched into the instruction register in q4. it is decoded and executed during the following q1 through q4. the clocks and instruction execution flow is shown in figure 3-3 and example 3-1. 3.2 instruction flow/pipelining an instruction cycle consists of four q cycles (q1, q2, q3 and q4). the instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute take another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the pc to change (e.g., goto ), then two cycles are required to complete the instruction (example 3-1). a fetch cycle begins with the pc incrementing in q1. in the execution cycle, the fetched instruction is latched into the instruction register (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3 and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). figure 3-3: clock /instruction cycle example 3-1: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc pc pc + 1 pc + 2 fetch inst (pc) execute inst (pc ? 1) fetch inst (pc + 1) execute inst (pc) fetch inst (pc + 2) execute inst (pc + 1) internal phase clock all instructions are single cycle, except for any program branches. these take two cycles, since the fetch instruction is ?flushed? from the pipeline, while the new instruction is being fetched and then executed. 1. movlw 03h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. call sub_1 fetch 3 execute 3 4. bsf portb, bit1 fetch 4 flush fetch sub_1 execute sub_1
? 2007 microchip technology inc. preliminary ds41236d-page 15 pic12f508/509/16f505 4.0 memory organization the pic12f508/509/16f505 memories are organized into program memory and data memory. for devices with more than 512 bytes of program memory, a paging scheme is used. program memory pages are accessed using one status register bit. for the pic12f509 and pic16f505, with data memory register files of more than 32 registers, a banking scheme is used. data memory banks are accessed using the file select register (fsr). 4.1 program memory organization for the pic12f508/509 the pic12f508 device has a 10-bit program counter (pc) and pic12f509 has a 11-bit program counter (pc) capable of addressing a 2k x 12 program memory space. only the first 512 x 12 (0000h-01ffh) for the pic12f508, and 1k x 12 (0000h-03ffh) for the pic12f509 are physically implemented (see figure 4-1). accessing a location above these boundaries will cause a wraparound within the first 512 x 12 space (pic12f508) or 1k x 12 space (pic12f509). the effective reset vector is a 0000h (see figure 4-1). location 01ffh (pic12f508) and location 03ffh (pic12f509) contain the internal clock oscillator calibration value. this value should never be overwritten. figure 4-1: program memory map and stack for the pic12f508/509 call, retlw pc<11:0> stack level 1 stack level 2 user memory space 12 0000h 7ffh 01ffh 0200h on-chip program memory reset vector (1) note 1: address 0000h becomes the effective reset vector. location 01ffh, 03ffh (pic12f508, pic12f509) contains the movlw xx internal oscillator calibration value. 512 word 1024 word 03ffh 0400h on-chip program memory
pic12f508/509/16f505 ds41236d-page 16 preliminary ? 2007 microchip technology inc. 4.2 program memory organization for the pic16f505 the pic16f505 device has a 11-bit program counter (pc) capable of addressing a 2k x 12 program memory space. the 1k x 12 (0000h-03ffh) for the pic16f505 are physically implemented. refer to figure 4-2. access- ing a location above this boundary will cause a wrap- around within the first 1k x 12 space. the effective reset vector is at 0000h (see figure 4-2). location 03ffh contains the internal oscillator calibration value. this value should never be overwritten. figure 4-2: program memory map and stack for the pic16f505 4.3 data memory organization data memory is composed of registers or bytes of ram. therefore, data memory for a device is specified by its register file. the register file is divided into two functional groups: special function registers (sfr) and general purpose registers (gpr). the special function registers include the tmr0 reg- ister, the program counter (pcl), the status register, the i/o registers (ports) and the file select register (fsr). in addition, special function registers are used to control the i/o port configuration and prescaler options. the general purpose registers are used for data and control information under command of the instructions. for the pic12f508/509, the register file is composed of 7 special function registers, 9 general purpose registers and 16 or 32 general purpose registers accessed by banking (see figure 4-3 and figure 4-4). for the pic16f505, the register file is composed of 8 special function registers, 8 general purpose registers and 64 general purpose registers accessed by banking (figure 4-5). 4.3.1 general purpose register file the general purpose register file is accessed, either directly or indirectly, through the file select register (fsr). see section 4.9 ?indirect data addressing: indf and fsr registers? . call, retlw pc<11:0> stack level 1 stack level 2 user memory space 12 0000h 7ffh 01ffh 0200h reset vector (1) note 1: address 0000h becomes the effective reset vector. location 03ffh contains the movlw xx internal oscillator calibration value. 1024 words 03ffh 0400h on-chip program memory
? 2007 microchip technology inc. preliminary ds41236d-page 17 pic12f508/509/16f505 figure 4-3: pic12f508 register file map figure 4-4: pic12f509 register file map figure 4-5: pic16f505 register file map file address 00h 01h 02h 03h 04h 05h 06h 07h 1fh indf (1) tmr0 pcl status fsr osccal gpio general purpose registers note 1: not a physical register. see section 4.9 ?indirect data addressing: indf and fsr registers? . file address 00h 01h 02h 03h 04h 05h 06h 07h 1fh indf (1) tmr0 pcl status fsr osccal gpio 0fh 10h bank 0 bank 1 3fh 30h 20h 2fh general purpose registers general purpose registers general purpose registers addresses map back to addresses in bank 0. note 1: not a physical register. see section 4.9 ?indirect data addressing: indf and fsr registers? . fsr<5> 0 1 file address 00h 01h 02h 03h 04h 05h 06h 07h 1fh indf (1) tmr0 pcl status fsr osccal portb 0fh 10h bank 0 bank 1 3fh 30h 20h 2fh general purpose registers general purpose registers general purpose registers addresses map back to addresses in bank 0. note 1: not a physical register. see section 4.9 ?indirect data addressing: indf and fsr registers? . fsr<6:5> 00 01 bank 3 7fh 70h 60h 6fh general purpose registers 11 bank 2 5fh 50h 40h 4fh general purpose registers 10 08h portc
pic12f508/509/16f505 ds41236d-page 18 preliminary ? 2007 microchip technology inc. 4.3.2 special function registers the special function registers (sfrs) are registers used by the cpu and peripheral functions to control the operation of the device (table 4-1). the special function registers can be classified into two sets. the special function registers associated with the ?core? functions are described in this section. those related to the operation of the peripheral features are described in the section for each peripheral feature. table 4-1: special function register (sfr) summary (pic12f508/509) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset (2) page # 00h indf uses contents of fsr to address data memory (not a physical register) xxxx xxxx 26 01h tmr0 8-bit real-time clock/counter xxxx xxxx 33 02h (1) pcl low-order 8 bits of pc 1111 1111 25 03h status gpwuf ?pa0 (5) to pd zdcc 0-01 1xxx (3) 20 04h fsr indirect data memory address pointer 111x xxxx 26 04h (4) fsr indirect data memory address pointer 110x xxxx 26 05h osccal cal6 cal5 cal4 cal3 cal2 cal1 cal0 ? 1111 111- 24 06h gpio ? ? gp5 gp4 gp3 gp2 gp1 gp0 --xx xxxx 29 n/a trisgpio ? ? i/o control register --11 1111 29 n/a option gpwu gppu tocs tose psa ps2 ps1 ps0 1111 1111 22 legend: ? = unimplemented, read as ? 0 ?, x = unknown, u = unchanged, q = value depends on condition. note 1: the upper byte of the program counter is not directly accessible. see section 4.7 ?program counter? for an explanation of how to access these bits. 2: other (non power-up) resets include external reset through mclr , watchdog timer and wake-up on pin change reset. 3: if reset was due to wake-up on pin change, then bit 7 = 1 . all other resets will cause bit 7 = 0 . 4: pic12f509 only. 5: this bit is used on the pic12f509. for code compatibility do not use this bit on the pic12f508.
? 2007 microchip technology inc. preliminary ds41236d-page 19 pic12f508/509/16f505 table 4-2: special function register (sfr) summary (pic16f505) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset (2) page # 00h indf uses contents of fsr to address data memory (not a physical register) xxxx xxxx 26 01h tmr0 8-bit real-time clock/counter xxxx xxxx 33 02h (1) pcl low-order 8 bits of pc 1111 1111 25 03h status rbwuf ?pa0to pd zdcc 0-01 1xxx 20 04h fsr indirect data memory address pointer 100x xxxx 26 05h osccal cal6 cal5 cal4 cal3 cal2 cal1 cal0 ? 1111 111- 24 06h portb ? ? rb5 rb4 rb3 rb2 rb1 rb0 --xx xxxx 29 07h portc ? ? rc5 rc4 rc3 rc2 rc1 rc0 --xx xxxx 29 n/a trisb ? ? i/o control register --11 1111 29 n/a trisc ? ? i/o control register --11 1111 29 n/a option rbwu rbpu tocs tose psa ps2 ps1 ps0 1111 1111 23 legend: ? = unimplemented, read as ? 0 ?, x = unknown, u = unchanged, q = value depends on condition. note 1: if reset was due to wake-up on pin change, then bit 7 = 1 . all other resets will cause bit 7 = 0 . 2: other (non power-up) resets include external reset through mclr , watchdog timer and wake-up on pin change reset.
pic12f508/509/16f505 ds41236d-page 20 preliminary ? 2007 microchip technology inc. 4.4 status register this register contains the arithmetic status of the alu, the reset status and the page preselect bit. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status, will clear the upper three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). therefore, it is recommended that only bcf , bsf and movwf instructions be used to alter the status regis- ter. these instructions do not affect the z, dc or c bits from the status register. for other instructions which do affect status bits, see section 8.0 ?instruction set summary? . register 4-1: status register (address: 03h) (pic12f508/509) r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x gpwuf ?pa0to pd zdcc bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 gpwuf: gpio reset bit 1 = reset due to wake-up from sleep on pin change 0 = after power-up or other reset bit 6 reserved : do not use bit 5 pa0 : program page preselect bits (1) 1 = page 1 (200h-3ffh) 0 = page 0 (000h-1ffh) each page is 512 bytes. using the pa0 bit as a general purpose read/write bit in dev ices which do not use it fo r program page preselect is not recommended, since this may affect upward compatibility with future products. bit 4 to : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc : digit carry/borrow bit (for addwf and subwf instructions) addwf: 1 = a carry from the 4th low-order bit of the result occurred 0 = a carry from the 4th low-order bit of the result did not occur subwf: 1 = a borrow from the 4th low-order bit of the result did not occur 0 = a borrow from the 4th low-order bit of the result occurred bit 0 c : carry/borrow bit (for addwf , subwf and rrf , rlf instructions) addwf: subwf: rrf or rlf: 1 = a carry occurred 1 = a borrow did not occur load bit with lsb or msb, respectively 0 = a carry did not occur 0 = a borrow occurred note 1: this bit is used on the pic12f509. for code compatibility do not use this bit on the pic12f508.
? 2007 microchip technology inc. preliminary ds41236d-page 21 pic12f508/509/16f505 register 4-2: status register (address: 03h) (pic16f505) r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x rbwuf ?pa0to pd zdcc bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 rbwuf: portb reset bit 1 = reset due to wake-up from sleep on pin change 0 = after power-up or other reset bit 6 reserved : do not use bit 5 pa0 : program page preselect bits 1 = page 1 (200h-3ffh) 0 = page 0 (000h-1ffh) each page is 512 bytes. using the pa0 bit as a general purpose read/write bit in devices which do not use it for program page preselect is not recommended, since this may affect upward compatibility with future products. bit 4 to : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc : digit carry/borrow bit (for addwf and subwf instructions) addwf: 1 = a carry from the 4th low-order bit of the result occurred 0 = a carry from the 4th low-order bit of the result did not occur subwf: 1 = a borrow from the 4th low-order bit of the result did not occur 0 = a borrow from the 4th low-order bit of the result occurred bit 0 c : carry/borrow bit (for addwf , subwf and rrf , rlf instructions) addwf : subwf : rrf or rlf : 1 = a carry occurred 1 = a borrow did not occur load bit with lsb or msb, respectively 0 = a carry did not occur 0 = a borrow occurred
pic12f508/509/16f505 ds41236d-page 22 preliminary ? 2007 microchip technology inc. 4.5 option register the option register is a 8-bit wide, write-only register, which contains various control bits to configure the timer0/wdt prescaler and timer0. by executing the option instruction, the contents of the w register will be transferred to the option regis- ter. a reset sets the option<7:0> bits. note: if tris bit is set to ? 0 ?, the wake-up on change and pull-up functions are disabled for that pin (i.e., note that tris overrides option control of gppu /rbpu and gpwu /rbwu ). note: if the t0cs bit is set to ? 1 ?, it will override the tris function on the t0cki pin. register 4-3: option register (pic12f508/509) w-1 w-1 w-1 w-1 w-1 w-1 w-1 w-1 gpwu gppu t0cs t0se psa ps2 ps1 ps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 gpwu : enable wake-up on pin change bit (gp0, gp1, gp3) 1 = disabled 0 = enabled bit 6 gppu : enable weak pull-ups bit (gp0, gp1, gp3) 1 = disabled 0 = enabled bit 5 t0cs : timer0 clock source select bit 1 = transition on t0cki pin (overrides tris on the t0cki pin) 0 = transition on internal instruction cycle clock, f osc /4 bit 4 t0se : timer0 source edge select bit 1 = increment on high-to-low transition on the t0cki pin 0 = increment on low-to-high transition on the t0cki pin bit 3 psa : prescaler assignment bit 1 = prescaler assigned to the wdt 0 = prescaler assigned to timer0 bit 2-0 ps<2:0>: prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value timer0 rate wdt rate
? 2007 microchip technology inc. preliminary ds41236d-page 23 pic12f508/509/16f505 register 4-4: option register (pic16f505) w-1 w-1 w-1 w-1 w-1 w-1 w-1 w-1 rbwu rbpu t0cs t0se psa ps2 ps1 ps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 rbwu : enable wake-up on pin change bit (rb0, rb1, rb3, rb4) 1 = disabled 0 = enabled bit 6 rbpu : enable weak pull-ups bit (rb0, rb1, rb3, rb4) 1 = disabled 0 = enabled bit 5 t0cs : timer0 clock source select bit 1 = transition on t0cki pin (overrides tris on the t0cki pin) 0 = transition on internal instruction cycle clock, f osc /4 bit 4 t0se : timer0 source edge select bit 1 = increment on high-to-low transition on the t0cki pin 0 = increment on low-to-high transition on the t0cki pin bit 3 psa : prescaler assignment bit 1 = prescaler assigned to the wdt 0 = prescaler assigned to timer0 bit 2-0 ps<2:0>: prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value timer0 rate wdt rate
pic12f508/509/16f505 ds41236d-page 24 preliminary ? 2007 microchip technology inc. 4.6 osccal register the oscillator calibration (osccal) register is used to calibrate the internal precision 4 mhz oscillator. it contains seven bits for calibration . after you move in the calibration constant, do not change the value. see section 7.2.5 ?internal 4 mhz rc oscillator? . note: erasing the device will also erase the pre- programmed internal calibration value for the internal oscillator. the calibration value must be read prior to erasing the part so it can be reprogrammed correctly later. register 4-5: osccal register (address: 05h) r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-0 cal6 cal5 cal4 cal3 cal2 cal1 cal0 ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-1 cal<6:0>: oscillator calibration bits 0111111 = maximum frequency ? ? ? 0000001 0000000 = center frequency 1111111 ? ? ? 1000000 = minimum frequency bit 0 unimplemented : read as ? 0 ?
? 2007 microchip technology inc. preliminary ds41236d-page 25 pic12f508/509/16f505 4.7 program counter as a program instruction is executed, the program counter (pc) will contain the address of the next program instruction to be executed. the pc value is increased by one every instruction cycle, unless an instruction changes the pc. for a goto instruction, bits 8:0 of the pc are provided by the goto instruction word. the program counter (pcl) is mapped to pc<7:0>. bit 5 of the status register provides page information to bit 9 of the pc (figure 4-6). for a call instruction, or any instruction where the pcl is the destination, bits 7:0 of the pc again are provided by the instruction word. however, pc<8> does not come from the instruction word, but is always cleared (figure 4-6). instructions where the pcl is the destination, or modify pcl instructions, include movwf pc, addwf pc and bsf pc,5. figure 4-6: loading of pc branch instructions 4.7.1 effects of reset the pc is set upon a reset, which means that the pc addresses the last location in the last page (i.e., the oscillator calibration instruction). after executing movlw xx , the pc will roll over to location 00h and begin executing user code. the status register page preselect bits are cleared upon a reset, which means that page 0 is pre-selected. therefore, upon a reset, a goto instruction will automatically cause the program to jump to page 0 until the value of the page bits is altered. 4.8 stack the pic12f508/509/16f505 devices have a 2-deep, 12-bit wide hardware push/pop stack. a call instruction will push the current value of stack 1 into stack 2 and then push the current pc value, incre- mented by one, into stack level 1. if more than two sequential call s are executed, only the most recent two return addresses are stored. a retlw instruction will pop the contents of stack level 1 into the pc and then copy stack level 2 contents into stack level 1. if more than two sequential retlw s are executed, the stack will be filled with the address previously stored in stack level 2. note that the w register will be loaded with the literal value specified in the instruction. this is particularly useful for the implementation of data look-up tables within the program memory. note: because pc<8> is cleared in the call instruction or any modify pcl instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any program memory page (512 words long). pa0 status pc 87 0 pcl 9 10 instruction word 7 0 goto instruction call or modify pcl instruction 11 pa0 status pc 87 0 pcl 9 10 instruction word 7 0 11 reset to ? 0 ? note 1: there are no status bits to indicate stack overflows or stack underflow conditions. 2: there are no instruction mnemonics called push or pop. these are actions that occur from the execution of the call and retlw instructions.
pic12f508/509/16f505 ds41236d-page 26 preliminary ? 2007 microchip technology inc. 4.9 indirect data addressing: indf and fsr registers the indf register is not a physical register. addressing indf actually addresses the register whose address is contained in the fsr register (fsr is a pointer ). this is indirect addressing. 4.9.1 indirect addressing ? register file 07 contains the value 10h ? register file 08 contains the value 0ah ? load the value 07 into the fsr register ? a read of the indf register will return the value of 10h ? increment the value of the fsr register by one (fsr = 08) ? a read of the indr register now will return the value of 0ah. reading indf itself indirectly (fsr = 0 ) will produce 00h. writing to the indf register indirectly results in a no operation (although status bits may be affected). a simple program to clear ram locations 10h-1fh using indirect addressing is shown in example 4-1. example 4-1: how to clear ram using indirect addressing the fsr is a 5-bit wide register. it is used in conjunction with the indf register to indirectly address the data memory area. the fsr<4:0> bits are used to select data memory addresses 00h to 1fh. figure 4-7: direct/indirect addressing (pic12f508/509) pic12f508 ? does not use banking. fsr <7:5> are unimplemented and read as ? 1 ?s. pic12f509 ? uses fsr<5>. selects between bank 0 and bank 1. fsr<7:6> are unimplemented, read as ? 1 ?. pic16f505 ? uses fsr<6:5>. selects from bank 0 to bank 3. fsr<7> is unimplemented, read as ? 1 ?. movlw 0x10 ;initialize p ointer movwf fsr ;to ram next clrf indf ;clear indf ;register incf fsr,f ;inc pointer btfsc fsr,4 ;all done? goto next ;no, clear next continue : ;yes, continue : note 1: for register map detail, see section 4.3 ?data memory organization? . 2: pic12f509. bank location select location select bank select indirect addressing direct addressing data memory (1) 0fh 10h bank 0 bank 1 (2) 0 4 5 6 (fsr) 00 01 00h 1fh 3fh (opcode) 0 4 5 6 (fsr) addresses map back to addresses in bank 0.
? 2007 microchip technology inc. preliminary ds41236d-page 27 pic12f508/509/16f505 figure 4-8: direct/indirect addressing (pic16f505) note 1: for register map detail, see section 4.3 ?data memory organization? . direct addressing (fsr) 6 5 4 (opcode) 0 bank select location select 00 01 10 11 00h 0fh 10h data memory (1) 1fh 3fh 5fh 7fh bank 0 bank 1 bank 2 bank 3 indirect addressing 6 5 4 (fsr) 0 bank location select addresses map back to addresses in bank 0.
pic12f508/509/16f505 ds41236d-page 28 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds41236d-page 29 pic12f508/509/16f505 5.0 i/o port as with any other register, the i/o register(s) can be written and read under program control. however, read instructions (e.g., movf portb,w ) always read the i/o pins independent of the pin?s input/output modes. on reset, all i/o ports are defined as input (inputs are at high-impedance) since the i/o control registers are all set. 5.1 portb/gpio portb/gpio is an 8-bit i/o register. only the low- order 6 bits are used (rb/gp<5:0>). bits 7 and 6 are unimplemented and read as ? 0 ?s. please note that rb3/ gp3 is an input only pin. the configuration word can set several i/o?s to alternate functions. when acting as alternate functions, the pins will read as ? 0 ? during a port read. pins rb0/gp0, rb1/gp1, rb3/gp3 and rb4 can be configured with weak pull-ups and also for wake-up on change. the wake-up on change and weak pull-up functions are not pin selectable. if rb3/gp3/ mclr is configured as mclr , weak pull-up is always on and wake-up on change for this pin is not enabled. 5.2 portc (pic16f505 only) portc is an 8-bit i/o register. only the low-order 6 bits are used (rc<5:0>). bits 7 and 6 are unimplemented and read as ? 0 ?s. 5.3 tris registers the output driver control register is loaded with the contents of the w register by executing the tris f instruction. a ? 1 ? from a tris register bit puts the corre- sponding output driver in a high-impedance mode. a ? 0 ? puts the contents of the output data latch on the selected pins, enabling the output buffer. the excep- tions are rb3/gp3, which is input only and the t0cki pin, which may be controlled by the option register. see register 4-3 and register 4-4. the tris registers are ?write-only? and are set (output drivers disabled) upon reset. 5.4 i/o interfacing the equivalent circuit for an i/o port pin is shown in figure 5-2. all port pins, except rb3/gp3 which is input only, may be used for both input and output oper- ations. for input operations, these ports are non-latch- ing. any input must be present until read by an input instruction (e.g., movf portb, w ). the outputs are latched and remain unchanged until the output latch is rewritten. to use a port pin as output, the correspond- ing direction control bit in tris must be cleared (= 0 ). for use as an input, the corresponding tris bit must be set. any i/o pin (except rb3/gp3) can be programmed individually as input or output. figure 5-1: pic12f508/509/16f505 equivalent circuit for a single i/o pin note: on the pic12f508/509, i/o portb is ref- erenced as gpio. on the pic16f505, i/o portb is referenced as portb. note: a read of the ports reads the pins, not the output data latches. that is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low. data bus q d q ck q d q ck p n wr port tris ?f? data tris rd port v ss v dd i/o pin w reg latch latch reset note 1: see table 3-3 for buffer type. v ss v dd (1)
pic12f508/509/16f505 ds41236d-page 30 preliminary ? 2007 microchip technology inc. table 5-1: summary of port registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets n/a trisgpio (1) ? ? i/o control register --11 1111 --11 1111 n/a trisb (2) ? ? i/o control register --11 1111 --11 1111 n/a trisc (2) ? ? i/o control register --11 1111 --11 1111 n/a option (1) gpwu gppu tocs tose psa ps2 ps1 ps0 1111 1111 1111 1111 n/a option (2) rbwu rbpu tocs tose psa ps2 ps1 ps0 1111 1111 1111 1111 03h status (1) gpwuf ? pao to pd z dc c 0-01 1xxx q00q quuu (3) 03h status (2) rbwuf ? pao to pd z dc c 0-01 1xxx q00q quuu (3) 06h gpio (1) ? ? gp5 gp4 gp3 gp2 gp1 gp0 --xx xxxx --uu uuuu 06h portb (2) ? ? rb5 rb4 rb3 rb2 rb1 rb0 --xx xxxx --uu uuuu 07h portc (2) ? ? rc5 rc4 rc3 rc2 rc1 rc0 --xx xxxx --uu uuuu legend: shaded cells are not used by po rt registers, read as ? 0 ?. ? = unimplemented, read as ? 0 ?, x = unknown, u = unchanged, q = depends on condition. note 1: pic12f508/509 only. 2: pic16f505 only. 3: if reset was due to wake-up on pin change, then bit 7 = 1 . all other resets will cause bit 7 = 0 .
? 2007 microchip technology inc. preliminary ds41236d-page 31 pic12f508/509/16f505 5.5 i/o programming considerations 5.5.1 bidirectional i/o ports some instructions operate internally as read followed by write operations. the bcf and bsf instructions, for example, read the entire port into the cpu, execute the bit operation and re-write the result. caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. for example, a bsf operation on bit 5 of portb/gpio will cause all eight bits of portb/gpio to be read into the cpu, bit 5 to be set and the portb/gpio value to be written to the output latches. if another bit of portb/ gpio is used as a bidirectional i/o pin (say bit 0 ) and it is defined as an input at this time, the input signal present on the pin itself would be read into the cpu and rewritten to the data latch of this particular pin, overwrit- ing the previous content. as long as the pin stays in the input mode, no problem occurs. however, if bit 0 is switched into output mode later on, the content of the data latch may now be unknown. example 5-1 shows the effect of two sequential read-modify-write instructions (e.g., bcf, bsf , etc.) on an i/o port. a pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin (?wired or?, ?wired and?). the resulting high output currents may damage the chip. example 5-1: read-modify-write instructions on an i/o port(e.g., pic16f505) 5.5.2 successive operations on i/o ports the actual write to an i/o port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (figure 5-2). therefore, care must be exercised if a write followed by a read operation is carried out on the same i/o port. the sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction causes that file to be read into the cpu. otherwise, the previous state of that pin may be read into the cpu rather than the new state. when in doubt, it is better to separate these instructions with a nop or another instruction not accessing this i/o port. figure 5-2: successive i/o operation (pic16f505 shown) ;initial portb settings ;portb<5:3> inputs ;portb<2:0> outputs ; ; portb latch portb pins ; ---------- ---------- bcf portb, 5 ;--01 -ppp --11 pppp bcf portb, 4 ;--10 -ppp --11 pppp movlw 007h; tris portb ;--10 -ppp --11 pppp ; note 1: the user may have expected the pin values to be ? --00 pppp ?. the 2nd bcf caused rb5 to be latched as the pin value (high). pc pc + 1 pc + 2 pc + 3 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction fetched rb<5:0> movwf portb nop port pin sampled here nop movf portb , w instruction executed movwf portb (write to portb) nop movf portb,w this example shows a write to portb followed by a read from portb. data setup time = (0.25 t cy ? t pd ) where: t cy = instruction cycle t pd = propagation delay therefore, at higher clock frequencies, a write followed by a read may be problematic. (read portb) port pin written here
pic12f508/509/16f505 ds41236d-page 32 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds41236d-page 33 pic12f508/509/16f505 6.0 timer0 module and tmr0 register the timer0 module has the following features: ? 8-bit timer/counter register, tmr0 ? readable and writable ? 8-bit software programmable prescaler ? internal or external clock select: - edge select for external clock figure 6-1 is a simplified block diagram of the timer0 module. timer mode is selected by clearing the t0cs bit (option<5>). in timer mode, the timer0 module will increment every instruction cycle (without prescaler). if tmr0 register is written, the increment is inhibited for the following two cycles (figure 6-2 and figure 6-3). the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting the t0cs bit (option<5>). in this mode, timer0 will increment either on every rising or falling edge of pin t0cki. the t0se bit (option<4>) determines the source edge. clearing the t0se bit selects the rising edge. restric- tions on the external clock input are discussed in detail in section6.1 ?using timer0 with an external clock? . the prescaler may be used by either the timer0 module or the watchdog timer, but not both. the prescaler assignment is controlled in software by the control bit, psa (option<3>). clearing the psa bit will assign the prescaler to timer0. the prescaler is not readable or writable. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. section 6.2 ?prescaler? details the operation of the prescaler. a summary of registers associated with the timer0 module is found in table 6-1. figure 6-1: timer0 block diagram figure 6-2: timer0 timing: in ternal clock/no prescale note 1: bits t0cs, t0se, psa, ps2, ps1 and ps0 are located in the option register. 2: the prescaler is shared with the watchdog timer (figure 6-5). 0 1 1 0 t0cs (1) f osc /4 programmable prescaler (2) sync with internal clocks tmr0 reg ps out (2 t cy delay) ps out data bus 8 psa (1) ps2, ps1, ps0 (1) 3 sync t0se (gp2/rc5)/t0cki pin pc ? 1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction fetch timer0 pc pc + 1 pc + 2 pc + 3 pc + 4 pc + 6 t0 t0 + 1 t0 + 2 nt0 nt0 + 1 nt0 + 2 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instruction executed pc + 5 pc (program counter)
pic12f508/509/16f505 ds41236d-page 34 preliminary ? 2007 microchip technology inc. figure 6-3: timer0 timing: internal clock/prescale 1:2 table 6-1: registers associated with timer0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets 01h tmr0 timer0 ? 8-bit real-time clock/counter xxxx xxxx uuuu uuuu n/a option (1) gpwu gppu t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 n/a option (2) rbwu rbpu t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 n/a trisgpio (1), (3) ? ? i/o control register --11 1111 --11 1111 n/a trisc (2), (3) ? ? rc5 rc4 rc3 rc2 rc1 rc0 --11 1111 --11 1111 legend: shaded cells are not used by timer0. ? = unimplemented, x = unknown, u = unchanged. note 1: pic12f508/509 only. 2: pic16f505 only. 3: the tris of the t0cki pin is overridden when t0cs = 1. pc ? 1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction fetch timer0 pc pc + 1 pc + 2 pc + 3 pc + 4 pc + 6 t0 t0 + 1 nt0 nt0 + 1 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instruction executed pc + 5 pc (program counter)
? 2007 microchip technology inc. preliminary ds41236d-page 35 pic12f508/509/16f505 6.1 using timer0 with an external clock when an external clock input is used for timer0, it must meet certain requirements. the external clock require- ment is due to internal phase clock (t osc ) synchroniza- tion. also, there is a delay in the actual incrementing of timer0 after synchronization. 6.1.1 external clock synchronization when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of t0cki with the internal phase clocks is accom- plished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks (figure 6-4). therefore, it is necessary for t0cki to be high for at least 2 t osc (and a small rc delay of 2 tt0h) and low for at least 2 t osc (and a small rc delay of 2 tt0h). refer to the electrical specification of the desired device. when a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler, so that the prescaler output is symmetrical. for the external clock to meet the sampling require- ment, the ripple counter must be taken into account. therefore, it is necessary for t0cki to have a period of at least 4 t osc (and a small rc delay of 4 tt0h) divided by the prescaler value. the only requirement on t0cki high and low time is that they do not violate the minimum pulse width requirement of tt0h. refer to parameters 40, 41 and 42 in the electrical specification of the desired device. 6.1.2 timer0 increment delay since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the timer0 module is actually incremented. figure 6-4 shows the delay from the external clock edge to the timer incrementing. figure 6-4: timer0 timing with external clock increment timer0 (q4) external clock input or q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 timer0 t0 t0 + 1 t0 + 2 small pulse misses sampling external clock/prescaler output after sampling (3) prescaler output (2) (1) note 1: delay from clock input change to timer0 increment is 3 t osc to 7 t osc . (duration of q = t osc ). therefore, the error in measuring the interval between two edges on timer0 input = 4 t osc max. 2: external clock if no prescaler selected; prescaler output otherwise. 3: the arrows indicate the points in time where sampling occurs.
pic12f508/509/16f505 ds41236d-page 36 preliminary ? 2007 microchip technology inc. 6.2 prescaler an 8-bit counter is available as a prescaler for the timer0 module or as a postscaler for the watchdog timer (wdt), respectively (see section 7.6 ?watch- dog timer (wdt)? ). for simplicity, this counter is being referred to as ?prescaler? throughout this data sheet. the psa and ps<2:0> bits (option<3:0>) determine prescaler assignment and prescale ratio. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf 1 , movwf 1, bsf 1 , x , etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the wdt. the prescaler is neither readable nor writable. on a reset, the prescaler contains all ? 0 ?s. 6.2.1 switching prescaler assignment the prescaler assignment is fully under software control (i.e., it can be changed ?on-the-fly? during pro- gram execution). to avoid an unintended device reset, the following instruction sequence (example 6-1) must be executed when changing the prescaler assignment from timer0 to the wdt. example 6-1: changing prescaler (timer0 wdt) to change the prescaler from the wdt to the timer0 module, use the sequence shown in example 6-2. this sequence must be used even if the wdt is disabled. a clrwdt instruction should be executed before switching the prescaler. example 6-2: changing prescaler (wdt timer0) note: the prescaler may be used by either the timer0 module or the wdt, but not both. thus, a prescaler assignment for the timer0 module means that there is no prescaler for the wdt and vice versa. clrwdt ;clear wdt clrf tmr0 ;clear tmr0 & prescaler movlw ?00xx1111?b ;these 3 lines (5, 6, 7) option ;are required only if ;desired clrwdt ;ps<2:0> are 000 or 001 movlw ?00xx1xxx?b ;set postscaler to option ;desired wdt rate clrwdt ;clear wdt and ;prescaler movlw ?xxxx0xxx? ;select tmr0, new ;prescale value and ;clock source option
? 2007 microchip technology inc. preliminary ds41236d-page 37 pic12f508/509/16f505 figure 6-5: block diagram of the timer0/wdt prescaler (1), (2) t cy (= f osc /4) sync 2 cycles tmr0 reg 8-bit prescaler 8-to-1 mux m mux watchdog timer psa 0 1 0 1 wdt time-out ps<2:0> 8 psa wdt enable bit 0 1 0 1 data bus 8 psa t0cs m u x m u x u x t0se (gp2/rc5)/t0cki pin note 1: t0cs, t0se, psa, ps<2:0> are bits in the option register. 2: t0cki is shared with pin rc5 on the pic16f505 and pin gp2 on the pic12f508/509.
pic12f508/509/16f505 ds41236d-page 38 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds41236d-page 39 pic12f508/509/16f505 7.0 special features of the cpu what sets a microcontroller apart from other proces- sors are special circuits that deal with the needs of real- time applications. the pic12f508/509/16f505 microcontrollers have a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power- saving operating modes and offer code protection. these features are: ? oscillator selection ? reset: - power-on reset (por) - device reset timer (drt) - wake-up from sleep on pin change ? watchdog timer (wdt) ? sleep ? code protection ? id locations ? in-circuit serial programming? ?clock out the pic12f508/509/16f505 devices have a watchdog timer, which can be shut off only through configuration bit wdte. it runs off of its own rc oscillator for added reliability. if using hs (pic16f505), xt or lp selectable oscillator options, there is always an 18 ms (nominal) delay provided by the device reset timer (drt), intended to keep the chip in reset until the crystal oscillator is stable. if using intrc or extrc, there is an 18 ms delay only on v dd power-up. with this timer on-chip, most applications need no external reset circuitry. the sleep mode is designed to offer a very low-current power-down mode. the user can wake-up from sleep through a change on input pins or through a watchdog timer time-out. several oscillator options are also made available to allow the part to fit the application, including an internal 4 mhz oscillator. the extrc oscillator option saves system cost while the lp crystal option saves power. a set of configuration bits are used to select various options. 7.1 configuration bits the pic12f508/509/16f505 configuration words consist of 12 bits. configuration bits can be programmed to select various device configurations. three bits are for the selection of the oscillator type; (two bits on the pic12f508/509), one bit is the watchdog timer enable bit, one bit is the mclr enable bit and one bit is for code protection (register 7-1, register 7-2).
pic12f508/509/16f505 ds41236d-page 40 preliminary ? 2007 microchip technology inc. register 7-1: co nfiguration word for pic12f508/509 (1) ? ? ? ? ? ? ? mclre cp wdte fosc1 fosc0 bit 11 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 11-5 unimplemented : read as ? 0 ? bit 4 mclre: gp3/mclr pin function select bit 1 = gp3/mclr pin function is mclr 0 = gp3/mclr pin function is digital input, mclr internally tied to v dd bit 3 cp : code protection bit 1 = code protection off 0 = code protection on bit 2 wdte: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0 fosc<1:0>: oscillator selection bits 11 = extrc = external rc oscillator 10 = intrc = internal rc oscillator 01 = xt oscillator 00 = lp oscillator note 1: refer to the ? pic12f508/509 memory programming specifications ? (ds41227) to determine how to access the configuration word. the configuration word is not user addressabl e during device operation.
? 2007 microchip technology inc. preliminary ds41236d-page 41 pic12f508/509/16f505 register 7-2: configurat ion word for pic16f505 (1) ? ? ? ? ? ? mclre cp wdte fosc2 fosc1 fosc0 bit 11 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 11-6 unimplemented : read as ? 0 ? bit 5 mclre: rb3/mclr pin function select bit 1 = rb3/mclr pin function is mclr 0 = rb3/mclr pin function is digital input, mclr internally tied to v dd bit 4 cp : code protection bit 1 = code protection off 0 = code protection on bit 3 wdte: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 2-0 fosc<1:0>: oscillator selection bits 111 = external rc oscillator/clkout function on rb4/osc2/clkout pin 110 = external rc oscillator/rb4 function on rb4/osc2/clkout pin 101 = internal rc oscillator/clkout function on rb4/osc2/clkout pin 100 = internal rc oscillator/rb4 function on rb4/osc2/clkout pin 011 = ec oscillator/rb4 function on rb4/osc2/clkout pin 010 = hs oscillator 001 = xt oscillator 000 = lp oscillator note 1: refer to the ? pic16f505 memory programming specifications ? (ds41226) to determine how to access the configuration word. the configuration word is not user addressable during device operation.
pic12f508/509/16f505 ds41236d-page 42 preliminary ? 2007 microchip technology inc. 7.2 oscillator configurations 7.2.1 oscillator types the pic12f508/509/16f505 devices can be operated in up to six different oscillator modes. the user can program up to three configuration bits (fosc<1:0> [pic12f508/509], fosc<2:0> [pic16f505]). to select one of these modes: ? lp: low-power crystal ? xt: crystal/resonator ? hs: high-speed crystal/resonator (pic16f505 only) ? intrc: internal 4 mhz oscillator ? extrc: external resistor/capacitor ? ec: external high-speed clock input (pic16f505 only) 7.2.2 crystal oscillator/ceramic resonators in hs (pic16f505), xt or lp modes, a crystal or ceramic resonator is connected to the (gp5/rb5)/ osc1/(clkin) and (gp4/rb4)/osc2/(clkout) pins to establish oscillation (figure 7-1). the pic12f508/ 509/16f505 oscillator designs require the use of a parallel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. when in hs (pic16f505), xt or lp modes, the device can have an external clock source drive the (gp5/rb5)/osc1/clkin pin (figure 7-2). when the part is used in this fashion, the output drive levels on the osc2 pin are very weak. this pin should be left open and unloaded. also, when using this mode, the external clock should observe the frequency limits for the clock mode chosen (hs, xt or lp). figure 7-1: crystal operation (or ceramic resonator) (hs, xt or lp osc configuration) figure 7-2: external clock input operation (hs, xt or lp osc configuration) table 7-1: capacitor selection for ceramic resonators ? pic12f508/509/16f505 (1) note 1: this device has been designed to per- form to the parameters of its data sheet. it has been tested to an electrical specification designed to determine its conformance with these parameters. due to process differences in the manufacture of this device, this device may have different performance charac- teristics than its earlier version. these differences may cause this device to perform differently in your application than the earlier version of this device. 2: the user should verify that the device oscillator starts and performs as expected. adjusting the loading capacitor values and/or the oscillator mode may be required. osc type resonator freq. cap. range c1 cap. range c2 xt 4.0 mhz 30 pf 30 pf hs (2) 16 mhz 10-47 pf 10-47 pf note 1: these values are for design guidance only. since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components. 2: pic16f505 only. note 1: see capacitor selection tables for recommended values of c1 and c2. 2: a series resistor (rs) may be required for at strip cut crystals. 3: rf approx. value = 10 m . c1 (1) c2 (1) xtal osc2 osc1 rf (3) sleep to internal logic rs (2) pic12f508/509 pic16f505 clock from ext. system osc1 osc2 pic16f505 open pic12f508/509
? 2007 microchip technology inc. preliminary ds41236d-page 43 pic12f508/509/16f505 table 7-2: capacitor selection for crystal oscillator ? pic12f508/509/16f505 (2) 7.2.3 external crystal oscillator circuit either a prepackaged oscillator or a simple oscillator circuit with ttl gates can be used as an external crystal oscillator circuit. prepackaged oscillators provide a wide operating range and better stability. a well-designed crystal oscillator will provide good perfor- mance with ttl gates. two types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance. figure 7-3 shows implementation of a parallel resonant oscillator circuit. the circuit is designed to use the fun- damental frequency of the crystal. the 74as04 inverter performs the 180-degree phase shift that a parallel oscillator requires. the 4.7 k resistor provides the negative feedback for stability. the 10 k potentiome- ters bias the 74as04 in the linear region. this circuit could be used for external oscillator designs. figure 7-3: external parallel resonant crystal oscillator circuit figure 7-4 shows a series resonant oscillator circuit. this circuit is also designed to use the fundamental frequency of the crystal. the inverter performs a 180- degree phase shift in a series resonant oscillator circuit. the 330 resistors provide the negative feedback to bias the inverters in their linear region. figure 7-4: external series resonant crystal oscillator circuit 7.2.4 external rc oscillator for timing insensitive applications, the rc device option offers additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resis- tor (r ext ) and capacitor (c ext ) values, and the operat- ing temperature. in addition to this, the oscillator frequency will vary from unit-to-unit due to normal pro- cess parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low c ext values. the user also needs to take into account variation due to tolerance of external r and c components used. figure 7-5 shows how the r/c combination is con- nected to the pic12f508/509/16f505 devices. for r ext values below 3.0 k , the oscillator operation may become unstable, or stop completely. for very high r ext values (e.g., 1 m ), the oscillator becomes sensitive to noise, humidity and leakage. thus, we recommend keeping r ext between 5.0 k and 100 k . osc type resonator freq. cap. range c1 cap. range c2 lp 32 khz (1) 15 pf 15 pf xt 200 khz 1 mhz 4 mhz 47-68 pf 15 pf 15 pf 47-68 pf 15 pf 15 pf hs (3) 20 mhz 15-47 pf 15-47 pf note 1: for v dd > 4.5v, c1 = c2 30 pf is recommended. 2: these values are for design guidance only. rs may be required to avoid over- driving crystals with low drive level specifi- cation. since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. 3: pic16f505 only. 20 pf +5v 20 pf 10k 4.7k 10k 74as04 xtal 10k 74as04 pic16f505 clkin to o t h e r devices pic12f508 pic12f509 330 74as04 74as04 pic16f505 clkin to other devices xtal 330 74as04 0.1 mf pic12f508 pic12f509
pic12f508/509/16f505 ds41236d-page 44 preliminary ? 2007 microchip technology inc. although the oscillator will operate with no external capacitor (c ext = 0 pf), we recommend using values above 20 pf for noise and stability reasons. with no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as pcb trace capacitance or package lead frame capacitance. section 10.0 ?electrical characteristics? shows rc frequency variation from part-to-part due to normal process variation. the variation is larger for larger val- ues of r (since leakage current variation will affect rc frequency more for large r) and for smaller values of c (since variation of input capacitance will affect rc frequency more). also, see the electrical specifications section for variation of oscillator frequency due to v dd for given r ext /c ext values, as well as frequency variation due to operating temperature for given r, c and v dd values. figure 7-5: external rc oscillator mode 7.2.5 internal 4 mhz rc oscillator the internal rc oscillator provides a fixed 4 mhz (nom- inal) system clock at v dd = 5v and 25c, (see section 10.0 ?electrical characteristics? for information on variation over voltage and temperature). in addition, a calibration instruction is programmed into the last address of memory, which contains the calibra- tion value for the internal rc oscillator. this location is always uncode protected, regardless of the code-pro- tect settings. this value is programmed as a movlw xx instruction where xx is the calibration value, and is placed at the reset vector. this will load the w register with the calibration value upon reset and the pc will then roll over to the users program at address 0x000. the user then has the option of writing the value to the osccal register (05h) or ignoring it. osccal, when written to with the calibration value, will ?trim? the internal oscillator to remove process variation from the oscillator frequency. for the pic12f508/509/16f505 devices, only bits <7:1> of osccal are implemented. bits cal6-cal0 are used for calibration. adjusting cal6-cal0 from ? 0000000 ? to ? 1111111 ? changes the clock speed. see register 4-5 for more information. v dd r ext c ext v ss osc1 internal clock pic16f505 n f osc /4 osc2/clkout pic12f508 pic12f509 note: erasing the device will also erase the pre- programmed internal calibration value for the internal oscillator. the calibration value must be read prior to erasing the part so it can be reprogrammed correctly later. note: the 0 bit of osccal is unimplemented and should be written as ? 0 ? when modify- ing osccal for compatibility with future devices.
? 2007 microchip technology inc. preliminary ds41236d-page 45 pic12f508/509/16f505 7.3 reset the device differentiates between various kinds of reset: ? power-on reset (por) ?mclr reset during normal operation ?mclr reset during sleep ? wdt time-out reset during normal operation ? wdt time-out reset during sleep ? wake-up from sleep on pin change some registers are not reset in any way, they are unknown on por and unchanged in any other reset. most other registers are reset to ?reset state? on power-on reset (por), mclr , wdt or wake-up on pin change reset during normal operation. they are not affected by a wdt reset during sleep or mclr reset during sleep, since these resets are viewed as resumption of normal operation. the exceptions to this are to , pd and rbwuf/gpwuf bits. they are set or cleared differently in different reset situations. these bits are used in software to determine the nature of reset. see table 7-4 for a full description of reset states of all registers. table 7-3: reset conditions for registers ? pic12f508/509 register address power-on reset mclr reset, wdt time-out, wake-up on pin change w? qqqq qqqu (1) qqqq qqqu (1) indf 00h xxxx xxxx uuuu uuuu tmr0 01h xxxx xxxx uuuu uuuu pc 02h 1111 1111 1111 1111 status 03h 0001 1xxx q00q quuu (2), (3) fsr (4) 04h 110x xxxx 11uu uuuu fsr (5) 04h 111x xxxx 111u uuuu osccal 05h 1111 111- uuuu uuu- gpio 06h --xx xxxx --uu uuuu option ? 1111 1111 1111 1111 tris ? --11 1111 --11 1111 legend: u = unchanged, x = unknown, ? = unimplemented bit, read as ? 0 ?, q = value depends on condition. note 1: bits <7:2> of w register contain oscillator calibration values due to movlw xx instruction at top of memory. 2: see table 7-5 for reset value for specific conditions. 3: if reset was due to wake-up on pin change, then bit 7 = 1 . all other resets will cause bit 7 = 0 . 4: pic12f509 only. 5: pic12f508 only.
pic12f508/509/16f505 ds41236d-page 46 preliminary ? 2007 microchip technology inc. table 7-4: reset conditions for registers ? pic16f505 table 7-5: reset condition for special registers register address power-on reset mclr reset, wdt time-out, wake-up on pin change w? qqqq qqqu (1) qqqq qqqu (1) indf 00h xxxx xxxx uuuu uuuu tmr0 01h xxxx xxxx uuuu uuuu pc 02h 1111 1111 1111 1111 status 03h 0001 1xxx q00q quuu (2), (3) fsr 04h 100x xxxx 1uuu uuuu osccal 05h 1111 111- uuuu uuu- portb 06h --xx xxxx --uu uuuu portc 07h --xx xxxx --uu uuuu option ? 1111 1111 1111 1111 trisb ? --11 1111 --11 1111 trisc ? --11 1111 --11 1111 legend: u = unchanged, x = unknown, ? = unimplemented bit, read as ? 0 ?, q = value depends on condition. note 1: bits <7:2> of w register contain oscillator calibration values due to movlw xx instruction at top of memory. 2: see table 7-5 for reset value for specific conditions. 3: if reset was due to wake-up on pin change, then bit 7 = 1 . all other resets will cause bit 7 = 0 . status addr: 03h pcl addr: 02h power-on reset 0001 1xxx 1111 1111 mclr reset during normal operation 000u uuuu 1111 1111 mclr reset during sleep 0001 0uuu 1111 1111 wdt reset during sleep 0000 0uuu 1111 1111 wdt reset normal operation 0000 uuuu 1111 1111 wake-up from sleep on pin change 1001 0uuu 1111 1111 legend: u = unchanged, x = unknown, ? = unimplemented bit, read as ? 0 ?.
? 2007 microchip technology inc. preliminary ds41236d-page 47 pic12f508/509/16f505 7.3.1 mclr enable this configuration bit, when unprogrammed (left in the ? 1 ? state), enables the external mclr function. when programmed, the mclr function is tied to the internal v dd and the pin is assigned to be an input only. see figure 7-6. figure 7-6: mclr select 7.4 power-on reset (por) the pic12f508/509/16f505 devices incorporate an on-chip power-on reset (por) circuitry, which provides an internal chip reset for most power-up situations. the on-chip por circuit holds the chip in reset until v dd has reached a high enough level for proper oper- ation. to take advantage of the internal por, program the (gp3/rb3)/mclr /v pp pin as mclr and tie through a resistor to v dd , or program the pin as (gp3/ rb3). an internal weak pull-up resistor is implemented using a transistor (refer to table 10-2 for the pull-up resistor ranges). this will eliminate external rc compo- nents usually needed to create a power-on reset. a maximum rise time for v dd is specified. see section 10.0 ?electrical characteristics? for details. when the devices start normal operation (exit the reset condition), device operating parameters (volt- age, frequency, temperature,...) must be met to ensure operation. if these conditions are not met, the devices must be held in reset until the operating parameters are met. a simplified block diagram of the on-chip power-on reset circuit is shown in figure 7-7. the power-on reset circuit and the device reset timer (see section 7.5 ?device reset timer (drt)? ) circuit are closely related. on power-up, the reset latch is set and the drt is reset. the drt timer begins counting once it detects mclr to be high. after the time-out period, which is typically 18 ms, it will reset the reset latch and thus end the on-chip reset signal. a power-up example where mclr is held low is shown in figure 7-8. v dd is allowed to rise and stabilize before bringing mclr high. the chip will actually come out of reset t drt msec after mclr goes high. in figure 7-9, the on-chip power-on reset feature is being used (mclr and v dd are tied together or the pin is programmed to be (gp3/rb3). the v dd is stable before the start-up timer times out and there is no prob- lem in getting a proper reset. however, figure 7-10 depicts a problem situation where v dd rises too slowly. the time between when the drt senses that mclr is high and when mclr and v dd actually reach their full value, is too long. in this situation, when the start-up timer times out, v dd has not reached the v dd (min) value and the chip may not function correctly. for such situations, we recommend that external rc circuits be used to achieve longer por delay times (figure 7-9). for additional information, refer to application notes an522 ?power-up considerations? (ds00522) and an607 ?power-up trouble shooting? (ds00607). (gp3/rb3)/mclr /v pp mclre internal mclr gpwu /rbwu note: when the devices start normal operation (exit the reset condition), device operat- ing parameters (voltage, frequency, tem- perature, etc.) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met.
pic12f508/509/16f505 ds41236d-page 48 preliminary ? 2007 microchip technology inc. figure 7-7: simplified block di agram of on-chip reset circuit figure 7-8: time-out sequ ence on power-up (mclr pulled low) figure 7-9: time-out sequ ence on power-up (mclr tied to v dd ): fast v dd rise time sq r q v dd (gp3/rb3)/mclr /v pp power-up detect por (power-on reset) wdt reset chip reset mclre wake-up on pin change reset start-up timer (10 s or 18 ms) wdt time-out pin change sleep mclr reset v dd mclr internal por drt time-out internal reset tdrt v dd mclr internal por drt time-out internal reset tdrt
? 2007 microchip technology inc. preliminary ds41236d-page 49 pic12f508/509/16f505 figure 7-10: time-out sequ ence on power-up (mclr tied to v dd ): slow v dd rise time v dd mclr internal por drt time-out internal reset tdrt v1 note: when v dd rises slowly, the t drt time-out expires long before v dd has reached its final value. in this example, the chip will reset properly if, and only if, v1 v dd min.
pic12f508/509/16f505 ds41236d-page 50 preliminary ? 2007 microchip technology inc. 7.5 device reset timer (drt) on the pic12f508/509/16f505 devices, the drt runs any time the device is powered up. drt runs from reset and varies based on oscillator selection and reset type (see table 7-6). the drt operates on an internal rc oscillator. the processor is kept in reset as long as the drt is active. the drt delay allows v dd to rise above v dd min. and for the oscillator to stabilize. oscillator circuits based on crystals or ceramic resona- tors require a certain time after power-up to establish a stable oscillation. the on-chip drt keeps the devices in a reset condition for approximately 18 ms after mclr has reached a logic high (v ih mclr ) level. programming (gp3/rb3)/mclr /v pp as mclr and using an external rc network connected to the mclr input is not required in most cases. this allows savings in cost-sensitive and/or space restricted applications, as well as allowing the use of the (gp3/rb3)/mclr /v pp pin as a general purpose input. the device reset time delays will vary from chip-to- chip due to v dd , temperature and process variation. see ac parameters for details. the drt will also be triggered upon a watchdog timer time-out from sleep. this is particularly important for applications using the wdt to wake from sleep mode automatically. reset sources are por, mclr , wdt time-out and wake-up on pin change. see section 7.9.2 ?wake-up from sleep?, notes 1, 2 and 3 . 7.6 watchdog timer (wdt) the watchdog timer (wdt) is a free running on-chip rc oscillator, which does not require any external components. this rc oscillator is separate from the external rc oscillator of the (gp5/rb5)/osc1/clkin pin and the internal 4 mhz oscillator. this means that the wdt will run even if the main processor clock has been stopped, for example, by execution of a sleep instruction. during normal operation or sleep, a wdt reset or wake-up reset, generates a device reset. the to bit (status<4>) will be cleared upon a watchdog timer reset. the wdt can be permanently disabled by program- ming the configuration wdte as a ? 0 ? (see section 7.1 ?configuration bits? ). refer to the pic12f508/509/ 16f505 programming specifications to determine how to access the configuration word. table 7-6: drt (device reset timer period) 7.6.1 wdt period the wdt has a nominal time-out period of 18 ms, (with no prescaler). if a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the wdt (under software control) by writing to the option register. thus, a time-out period of a nominal 2.3 seconds can be realized. these peri- ods vary with temperature, v dd and part-to-part pro- cess variations (see dc specs). under worst case conditions (v dd = min., temperature = max., max. wdt prescaler), it may take several seconds before a wdt time-out occurs. 7.6.2 wdt programming considerations the clrwdt instruction clears the wdt and the postscaler, if assigned to the wdt, and prevents it from timing out and generating a device reset. the sleep instruction resets the wdt and the postscaler, if assigned to the wdt. this gives the maximum sleep time before a wdt wake-up reset. oscillator configuration por reset subsequent resets intosc, extrc 18 ms (typical) 10 s (typical) hs (1) , xt, lp 18 ms (typical) 18 ms (typical) ec (1) 18 ms (typical) 10 s (typical) note 1: pic16f505 only.
? 2007 microchip technology inc. preliminary ds41236d-page 51 pic12f508/509/16f505 figure 7-11: watchdo g timer block diagram table 7-7: summary of registers as sociated with the watchdog timer address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets n/a option (1) gpwu gppu t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 n/a option (2) rbwu rbpu t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: shaded boxes = not used by watchdog timer. ? = unimplemented, read as ? 0 ?, u = unchanged. note 1: pic12f508/509 only. 2: pic16f505 only. (figure 6-5) postscaler note 1: t0cs, t0se, psa, ps<2:0> are bits in the option register. wdt time-out watchdog time from timer0 clock source wdt enable configuration bit psa postscaler 8-to-1 mux ps<2:0> (figure 6-4) to timer0 0 1 m u x 1 0 psa mux
pic12f508/509/16f505 ds41236d-page 52 preliminary ? 2007 microchip technology inc. 7.7 time-out sequence, power-down and wake-up from sleep status bits (to , pd , gpwuf/rbwuf) the to , pd and (gpwuf/rbwuf) bits in the status register can be tested to determine if a reset condition has been caused by a power-up condition, a mclr or watchdog timer (wdt) reset. table 7-8: to /pd /(gpwuf/rbwuf) status after reset 7.8 reset on brown-out a brown-out is a condition where device power (v dd ) dips below its minimum value, but not to zero, and then recovers. the device should be reset in the event of a brown-out. to reset pic12f508/509/16f505 devices when a brown-out occurs, external brown-out protection circuits may be built, as shown in figure 7-12 and figure 7-13. figure 7-12: brown-out protection circuit 1 figure 7-13: brown-out protection circuit 2 figure 7-14: brown-out protection circuit 3 gpwuf/ rbwuf to pd reset caused by 000 wdt wake-up from sleep 00u wdt time-out (not from sleep) 010 mclr wake-up from sleep 011 power-up 0uu mclr not during sleep 110 wake-up from sleep on pin change legend: u = unchanged note 1: the to , pd and gpwuf/rbwuf bits maintain their status ( u ) until a reset occurs. a low-pulse on the mclr input does not change the to , pd and gpwuf/rbwuf status bits. note 1: this circuit will activate reset when v dd goes below vz + 0.7v (where vz = zener voltage). 2: pin must be confirmed as mclr . 33k 10k 40k (1) v dd mclr (2) pic16f505 v dd q1 pic12f508 pic12f509 note 1: this brown-out circuit is less expensive, although less accurate. transistor q1 turns off when v dd is below a certain level such that: 2: pin must be confirmed as mclr . v dd ? r1 r1 + r2 = 0.7v r2 40k (1) v dd mclr (2) pic16f505 r1 q1 v dd pic12f508 pic12f509 note: this brown-out protection circuit employs microchip technology?s mcp809 micro- controller supervisor. there are 7 different trip point selections to accommodate 5v to 3v systems. mclr pic16f505 v dd v dd v ss rst mcp809 v dd bypass capacitor pic12f508 pic12f509
? 2007 microchip technology inc. preliminary ds41236d-page 53 pic12f508/509/16f505 7.9 power-down mode (sleep) a device may be powered down (sleep) and later powered up (wake-up from sleep). 7.9.1 sleep the power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the to bit (status<4>) is set, the pd bit (status<3>) is cleared and the oscillator driver is turned off. the i/o ports maintain the status they had before the sleep instruction was executed (driving high, driving low or high-impedance). for lowest current consumption while powered down, the t0cki input should be at v dd or v ss and the (gp3/rb3)/mclr /v pp pin must be at a logic high level if mclr is enabled. 7.9.2 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. an external reset input on (gp3/rb3)/mclr / v pp pin, when configured as mclr . 2. a watchdog timer time-out reset (if wdt was enabled). 3. a change on input pin gp0/rb0, gp1/rb1, gp3/rb3 or rb4 when wake-up on change is enabled. these events cause a device reset. the to , pd and gpwuf/rbwuf bits can be used to determine the cause of device reset. the to bit is cleared if a wdt time-out occurred (and caused wake-up). the pd bit, which is set on power-up, is cleared when sleep is invoked. the gpwuf/rbwuf bit indicates a change in state while in sleep at pins gp0/rb0, gp1/rb1, gp3/rb3 or rb4 (since the last file or bit operation on gp/rb port). the wdt is cleared when the device wakes from sleep, regardless of the wake-up source. 7.10 program verification/code protection if the code protection bit has not been programmed, the on-chip program memory can be read out for verification purposes. the first 64 locations and the last location (osccal) can be read, regardless of the code protection bit setting. the last memory location can be read regardless of the code protection bit setting on the pic12f508/509/ 16f505 devices. 7.11 id locations four memory locations are designated as id locations where the user can store checksum or other code identification numbers. these locations are not accessible during normal execution, but are readable and writable during program/verify. use only the lower 4 bits of the id locations and always program the upper 8 bits as ? 0 ?s. 7.12 in-circuit serial programming? the pic12f508/509/16f505 microcontrollers can be serially programmed while in the end application circuit. this is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. this allows customers to manu- facture boards with unprogrammed devices and then program the microcontroller just before shipping the product. this also allows the most recent firmware, or a custom firmware, to be programmed. the devices are placed into a program/verify mode by holding the gp1/rb1 and gp0/rb0 pins low while rais- ing the mclr (v pp ) pin from v il to v ihh (see program- ming specification). gp1/rb1 becomes the programming clock and gp0/rb0 becomes the programming data. both gp1/rb1 and gp0/rb0 are schmitt trigger inputs in this mode. after reset, a 6-bit command is then supplied to the device. depending on the command, 14 bits of program data are then supplied to or from the device, depending if the command was a load or a read. for complete details of serial programming, please refer to the pic12f508/509/16f505 programming specifications. a typical in-circuit serial programming connection is shown in figure 7-15. note: a reset generated by a wdt time-out does not drive the mclr pin low. note: caution: right before entering sleep, read the input pins. when in sleep, wake- up occurs when the values at the pins change from the state they were in at the last reading. if a wake-up on change occurs and the pins are not read before re- entering sleep, a wake-up will occur immediately even if no pins change while in sleep mode.
pic12f508/509/16f505 ds41236d-page 54 preliminary ? 2007 microchip technology inc. figure 7-15: typical in-circuit serial programming connection external connector signals to n o r m a l connections to n o r m a l connections pic16f505 v dd v ss mclr /v pp gp1/rb1 gp0/rb0 +5v 0v v pp clk data i/o v dd pic12f508 pic12f509
? 2007 microchip technology inc. preliminary ds41236d-page 55 pic12f508/509/16f505 8.0 instruction set summary the pic16 instruction set is highly orthogonal and is comprised of three basic categories. ? byte-oriented operations ? bit-oriented operations ? literal and control operations each pic16 instruction is a 12-bit word divided into an opcode , which specifies the instruction type, and one or more operands which further specify the operation of the instruction. the formats for each of the catego- ries is presented in figure 8-1, while the various opcode fields are summarized in table 8-1. for byte-oriented instructions, ?f? represents a file reg- ister designator and ?d? represents a destination desig- nator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed in the file register specified in the instruction. for bit-oriented instructions, ?b? represents a bit field designator which selects the number of the bit affected by the operation, while ?f? represents the number of the file in which the bit is located. for literal and control operations, ?k? represents an 8 or 9-bit constant or literal value. table 8-1: opcode field descriptions all instructions are executed within a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles. one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 s. if a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. figure 8-1 shows the three general formats that the instructions can have. all examples in the figure use the following format to represent a hexadecimal number: 0xhhh where ?h? signifies a hexadecimal digit. figure 8-1: general format for instructions field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don?t care location (= 0 or 1 ) the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0 (store result in w) d = 1 (store result in file register ?f?) default is d = 1 label label name tos top-of-stack pc program counter wdt watchdog timer counter to time-out bit pd power-down bit dest destination, either the w register or the specified register file location [ ] options ( ) contents assigned to < > register bit field in the set of italics user defined term (font is courier) byte-oriented file register operations 11 6 5 4 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 5-bit file register address bit-oriented file register operations 11 8 7 5 4 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 5-bit file register address literal and control operations (except goto ) 11 8 7 0 opcode k (literal) k = 8-bit immediate value literal and control operations ? goto instruction 11 9 8 0 opcode k (literal) k = 9-bit immediate value
pic12f508/509/16f505 ds41236d-page 56 preliminary ? 2007 microchip technology inc. table 8-2: instruction set summary mnemonic, operands description cycles 12-bit opcode status affected notes msb lsb addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f ? f, d f, d f, d f, d f, d f, d f, d f ? f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap f exclusive or w with f 1 1 1 1 1 1 1 (2) 1 1 (2) 1 1 1 1 1 1 1 1 1 0001 0001 0000 0000 0010 0000 0010 0010 0011 0001 0010 0000 0000 0011 0011 0000 0011 0001 11df 01df 011f 0100 01df 11df 11df 10df 11df 00df 00df 001f 0000 01df 00df 10df 10df 10df ffff ffff ffff 0000 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c, dc, z z z z z z none z none z z none none c c c, dc, z none z 1, 2, 4 2, 4 4 2, 4 2, 4 2, 4 2, 4 2, 4 2, 4 1, 4 2, 4 2, 4 1, 2, 4 2, 4 2, 4 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 0100 0101 0110 0111 bbbf bbbf bbbf bbbf ffff ffff ffff ffff none none none none 2, 4 2, 4 literal and control operations andlw call clrwdt goto iorlw movlw option retlw sleep tris xorlw k k ? k k k ? k ? f k and literal with w call subroutine clear watchdog timer unconditional branch inclusive or literal with w move literal to w load option register return, place literal in w go into standby mode load tris register exclusive or literal to w 1 2 1 2 1 1 1 2 1 1 1 1110 1001 0000 101k 1101 1100 0000 1000 0000 0000 1111 kkkk kkkk 0000 kkkk kkkk kkkk 0000 kkkk 0000 0000 kkkk kkkk kkkk 0100 kkkk kkkk kkkk 0010 kkkk 0011 0fff kkkk z none to , pd none z none none none to , pd none z 1 3 note 1: the 9th bit of the program counter will be forced to a ? 0 ? by any instruction that writes to the pc except for goto . see section 4.7 ?program counter? . 2: when an i/o register is modified as a function of itself (e.g. movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 3: the instruction tris f , where f = 6, causes the contents of the w register to be written to the tri-state latches of portb. a ? 1 ? forces the pin to a high-impedance state and disables the output buffers. 4: if this instruction is executed on the tmr0 register (and, where applicable, d = 1 ), the prescaler will be cleared (if assigned to tmr0).
? 2007 microchip technology inc. preliminary ds41236d-page 57 pic12f508/509/16f505 addwf add w and f syntax: [ label ] addwf f,d operands: 0 f 31 d [ 0 , 1 ] operation: (w) + (f) (dest) status affected: c, dc, z description: add the contents of the w register and register ?f?. if ?d? is? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w).and. (k) (w) status affected: z description: the contents of the w register are and?ed with the eight-bit literal ?k?. the result is placed in the w register. andwf and w with f syntax: [ label ] andwf f,d operands: 0 f 31 d [0,1] operation: (w) .and. (f) (dest) status affected: z description: the contents of the w register are and?ed with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 31 0 b 7 operation: 0 (f) status affected: none description: bit ?b? in register ?f? is cleared. bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 31 0 b 7 operation: 1 (f) status affected: none description: bit ?b? in register ?f? is set. btfsc bit test f, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 31 0 b 7 operation: skip if (f) = 0 status affected: none description: if bit ?b? in register ?f? is ? 0 ?, then the next instruction is skipped. if bit ?b? is ? 0 ?, then the next instruc- tion fetched during the current instruction execution is discarded, and a nop is executed instead, making this a two-cycle instruction.
pic12f508/509/16f505 ds41236d-page 58 preliminary ? 2007 microchip technology inc. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 f 31 0 b < 7 operation: skip if (f) = 1 status affected: none description: if bit ?b? in register ?f? is ? 1 ?, then the next instruction is skipped. if bit ?b? is ? 1 ?, then the next instruc- tion fetched during the current instruction execution, is discarded and a nop is executed instead, making this a two-cycle instruction. call subroutine call syntax: [ label ] call k operands: 0 k 255 operation: (pc) + 1 top-of-stack; k pc<7:0>; (status<6:5>) pc<10:9>; 0 pc<8> status affected: none description: subroutine call. first, return address (pc + 1) is pushed onto the stack. the eight-bit immediate address is loaded into pc bits <7:0>. the upper bits pc<10:9> are loaded from status<6:5>, pc<8> is cleared. call is a two-cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 f 31 operation: 00h (f); 1 z status affected: z description: the contents of register ?f? are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h (w); 1 z status affected: z description: the w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h wdt; 0 wdt prescaler (if assigned); 1 to; 1 pd status affected: to , pd description: the clrwdt instruction resets the wdt. it also resets the prescaler, if the prescaler is assigned to the wdt and not timer0. status bits to and pd are set. comf complement f syntax: [ label ] comf f,d operands: 0 f 31 d [0,1] operation: (f ) (dest) status affected: z description: the contents of register ?f? are complemented. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?.
? 2007 microchip technology inc. preliminary ds41236d-page 59 pic12f508/509/16f505 decf decrement f syntax: [ label ] decf f,d operands: 0 f 31 d [0,1] operation: (f) ? 1 (dest) status affected: z description: decrement register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 31 d [0,1] operation: (f) ? 1 d; skip if result = 0 status affected: none description: the contents of register ?f? are decremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 0 ?, the next instruc- tion, which is already fetched, is discarded and a nop is executed instead making it a two-cycle instruction. goto unconditional branch syntax: [ label ] goto k operands: 0 k 511 operation: k pc<8:0>; status<6:5> pc<10:9> status affected: none description: goto is an unconditional branch. the 9-bit immediate value is loaded into pc bits <8:0>. the upper bits of pc are loaded from status<6:5>. goto is a two- cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 f 31 d [0,1] operation: (f) + 1 (dest) status affected: z description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 31 d [0,1] operation: (f) + 1 (dest), skip if result = 0 status affected: none description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 0 ?, then the next instruction, which is already fetched, is discarded and a nop is executed instead making it a two-cycle instruction. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. (k) (w) status affected: z description: the contents of the w register are or?ed with the eight-bit literal ?k?. the result is placed in the w register.
pic12f508/509/16f505 ds41236d-page 60 preliminary ? 2007 microchip technology inc. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 f 31 d [0,1] operation: (w).or. (f) (dest) status affected: z description: inclusive or the w register with register ?f?. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. movf move f syntax: [ label ] movf f,d operands: 0 f 31 d [0,1] operation: (f) (dest) status affected: z description: the contents of register ?f? are moved to destination ?d?. if ?d? is ? 0 ?, destination is the w register. if ?d? is ? 1 ?, the destination is file register ?f?. ?d? = 1 is useful as a test of a file register, since status flag z is affected. movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k (w) status affected: none description: the eight-bit literal ?k? is loaded into the w register. the ?don?t cares? will assembled as ? 0 ?s. movwf move w to f syntax: [ label ] movwf f operands: 0 f 31 operation: (w) (f) status affected: none description: move data from the w register to register ?f?. nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none description: no operation. option load option register syntax: [ label ] option operands: none operation: (w) option status affected: none description: the content of the w register is loaded into the option register.
? 2007 microchip technology inc. preliminary ds41236d-page 61 pic12f508/509/16f505 retlw return with literal in w syntax: [ label ] retlw k operands: 0 k 255 operation: k (w); tos pc status affected: none description: the w register is loaded with the eight-bit literal ?k?. the program counter is loaded from the top of the stack (the return address). this is a two-cycle instruction. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 f 31 d [0,1] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the left through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 f 31 d [0,1] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the right through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. c register ?f? c register ?f? sleep enter sleep mode syntax: [ label ] sleep operands: none operation: 00h wdt; 0 wdt prescaler; 1 to ; 0 pd status affected: to , pd, rbwuf description: time-out status bit (to ) is set. the power-down status bit (pd ) is cleared. rbwuf is unaffected. the wdt and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. see section 7.9 ?power-down mode (sleep)? on sleep for more details. subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 f 31 d [0,1] operation: (f) ? (w) ( dest) status affected: c, dc, z description: subtract (2?s complement method) the w register from register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 f 31 d [0,1] operation: (f<3:0>) (dest<7:4>); (f<7:4>) (dest<3:0>) status affected: none description: the upper and lower nibbles of register ?f? are exchanged. if ?d? is ? 0 ?, the result is placed in w register. if ?d? is ? 1 ?, the result is placed in register ?f?.
pic12f508/509/16f505 ds41236d-page 62 preliminary ? 2007 microchip technology inc. tris load tris register syntax: [ label ] tris f operands: f = 6 operation: (w) tris register f status affected: none description: tris register ?f? (f = 6 or 7) is loaded with the contents of the w register xorlw exclusive or literal with w syntax: [ label ]xorlw k operands: 0 k 255 operation: (w) .xor. k ( w) status affected: z description: the contents of the w register are xor?ed with the eight-bit literal ?k?. the result is placed in the w register. xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 f 31 d [0,1] operation: (w) .xor. (f) ( dest) status affected: z description: exclusive or the contents of the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?.
? 2007 microchip technology inc. preliminary ds41236d-page 63 pic12f508/509/16f505 9.0 development support the pic ? microcontrollers are supported with a full range of hardware and software development tools: ? integrated development environment - mplab ? ide software ? assemblers/compilers/linkers - mpasm tm assembler - mplab c18 and mplab c30 c compilers -mplink tm object linker/ mplib tm object librarian - mplab asm30 assembler/linker/library ? simulators - mplab sim software simulator ?emulators - mplab ice 2000 in-circuit emulator - mplab real ice? in-circuit emulator ? in-circuit debugger - mplab icd 2 ? device programmers - picstart ? plus development programmer - mplab pm3 device programmer - pickit? 2 development programmer ? low-cost demonstration and development boards and evaluation kits 9.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. the mplab ide is a windows ? operating system-based application that contains: ? a single graphical interface to all debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color-coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? visual device initializer for easy register initialization ? mouse over variable inspection ? drag and drop variables from source to watch windows ? extensive on-line help ? integration of select third party tools, such as hi-tech software c compilers and iar c compilers the mplab ide allows you to: ? edit your source files (either assembly or c) ? one touch assemble (or compile) and download to pic mcu emulator and simulator tools (automatically updates all project information) ? debug using: - source files (assembly or c) - mixed assembly and c - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power.
pic12f508/509/16f505 ds41236d-page 64 preliminary ? 2007 microchip technology inc. 9.2 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for all pic mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process 9.3 mplab c18 and mplab c30 c compilers the mplab c18 and mplab c30 code development systems are complete ansi c compilers for microchip?s pic18 and pic24 families of microcontrol- lers and the dspic30 and dspic33 family of digital sig- nal controllers. these compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 9.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 9.5 mplab asm30 assembler, linker and librarian mplab asm30 assembler produces relocatable machine code from symbolic assembly language for dspic30f devices. mplab c30 c compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: ? support for the entire dspic30f instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility 9.6 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c18 and mplab c30 c compilers, and the mpasm and mplab asm30 assemblers. the software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.
? 2007 microchip technology inc. preliminary ds41236d-page 65 pic12f508/509/16f505 9.7 mplab ice 2000 high-performance in-circuit emulator the mplab ice 2000 in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for pic microcontrollers. software control of the mplab ice 2000 in-circuit emulator is advanced by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator system with enhanced trace, trigger and data monitor- ing features. interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. the architecture of the mplab ice 2000 in-circuit emulator allows expansion to support new pic microcontrollers. the mplab ice 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft ? windows ? 32-bit operating system were chosen to best make these features available in a simple, unified application. 9.8 mplab real ice in-circuit emulator system mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc ? and mcu devices. it debugs and programs pic ? and dspic ? flash microcontrollers with the easy-to-use, powerful graphical user interface of the mplab integrated development environment (ide), included with each kit. the mplab real ice probe is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with the popular mplab icd 2 system (rj11) or with the new high speed, noise tolerant, low- voltage differential signal (lvds) interconnection (cat5). mplab real ice is field upgradeable through future firmware downloads in mplab ide. in upcoming releases of mplab ide, new devices will be supported, and new features will be added, such as software break- points and assembly code trace. mplab real ice offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 9.9 mplab icd 2 in-circuit debugger microchip?s in-circuit debugger, mplab icd 2, is a powerful, low-cost, run-time development tool, connecting to the host pc via an rs-232 or high-speed usb interface. this tool is based on the flash pic mcus and can be used to develop for these and other pic mcus and dspic dscs. the mplab icd 2 utilizes the in-circuit debugging capability built into the flash devices. this feature, along with microchip?s in-circuit serial programming tm (icsp tm ) protocol, offers cost- effective, in-circuit flash debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by setting breakpoints, single step- ping and watching variables, and cpu status and peripheral registers. running at full speed enables testing hardware and applications in real time. mplab icd 2 also serves as a development programmer for selected pic devices. 9.10 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various package types. the icsp? cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an sd/mmc card for file storage and secure data applications.
pic12f508/509/16f505 ds41236d-page 66 preliminary ? 2007 microchip technology inc. 9.11 picstart plus development programmer the picstart plus development programmer is an easy-to-use, low-cost, prototype programmer. it connects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer supports most pic devices in dip packages up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. 9.12 pickit 2 development programmer the pickit? 2 development programmer is a low-cost programmer and selected flash device debugger with an easy-to-use interface for programming many of microchip?s baseline, mid-range and pic18f families of flash memory microcontrollers. the pickit 2 starter kit includes a prototyping development board, twelve sequential lessons, software and hi-tech?s picc? lite c compiler, and is designed to help get up to speed quickly using pic ? microcontrollers. the kit provides everything needed to program, evaluate and develop applications using microchip?s powerful, mid-range flash memory family of microcontrollers. 9.13 demonstration, development and evaluation boards a wide variety of demonstration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart ? battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. check the microchip web page (www.microchip.com) and the latest ?product selector guide? (ds00148) for the complete list of demonstration, development and evaluation kits.
? 2007 microchip technology inc. preliminary ds41236d-page 67 pic12f508/509/16f505 10.0 electrical characteristics absolute maximum ratings (?) ambient temperature under bias................................................................................................. ......... -40c to +125c storage temperature ............................................................................................................ ................ -65c to +150c voltage on v dd with respect to v ss ............................................................................................................... 0 to +6.5v voltage on mclr with respect to v ss ..........................................................................................................0 to +13.5v voltage on all other pins with respect to v ss ............................................................................... -0.3v to (v dd + 0.3v) total power dissipation (1) ............................................................................................................................... ... 800 mw max. current out of v ss pin ........................................................................................................................... ..... 200 ma max. current into v dd pin ........................................................................................................................... ........ 150 ma input clamp current, i ik (v i < 0 or v i > v dd ) ................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ........................................................................................................... 20 ma max. output current sunk by any i/o pin ........................................................................................ ...................... 25 ma max. output current sourced by any i/o pin ..................................................................................... .................... 25 ma max. output current sourced by i/o port ....................................................................................... ....................... 75 ma max. output current sunk by i/o port .......................................................................................... ......................... 75 ma note 1: power dissipation is calculated as follows: p dis = v dd x {i dd ? i oh } + {(v dd ? v oh ) x i oh } + (v ol x i ol ) ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic12f508/509/16f505 ds41236d-page 68 preliminary ? 2007 microchip technology inc. figure 10-1: pic12f508/509/16f505 voltage-frequency graph, -40 c t a +125 c figure 10-2: maximum oscillator frequency table 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 410 frequency (mhz) v dd 20 (volts) 25 2.0 8 (pic16f505 only) 0 200 khz 4 mhz 20 mhz frequency (mhz) hs (1) extrc xt lp oscillator mode ec (1) intosc note 1: for pic16f505 only.
? 2007 microchip technology inc. preliminary ds41236d-page 69 pic12f508/509/16f505 10.1 dc characteristics: pic12f508/509/16f505 (industrial) dc characteristics standard operating conditions (unless otherwise specified) operating temperature -40 c t a +85 c (industrial) param no. sym. characteristic min. typ (1) max. units conditions d001 v dd supply voltage 2.0 5.5 v see figure 10-1 d002 v dr ram data retention voltage (2) ? 1.5* ? v device in sleep mode d003 v por v dd start voltage to ensure power-on reset ? vss ? v see section 7.4 "power-on reset (por)" for details d004 s vdd v dd rise rate to ensure power-on reset 0.05* ? ? v/ms see section 7.4 "power-on reset (por)" for details d010 i dd supply current (3,4) ? ? 175 0.625 275 1.1 a ma f osc = 4 mhz, v dd = 2.0v f osc = 4 mhz, v dd = 5.0v ? ? 500 1.5 650 2.2 a ma f osc = 10 mhz, v dd = 3.0v f osc = 20 mhz, v dd = 5.0v (pic16f505 only) ? ? 11 38 15 52 a a f osc = 32 khz, v dd = 2.0v f osc = 32 khz, v dd = 5.0v d020 i pd power-down current (5) ? ? 0.1 0.35 1.2 2.4 a a v dd = 2.0v v dd = 5.0v d022 i wdt wdt current (5) ? ? 1.0 7.0 3.0 16.0 a a v dd = 2.0v v dd = 5.0v * these parameters are characterized but not tested. note 1: data in the typical (?typ?) column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. 4: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. 5: for standby current measurements, the conditions are the same as idd, except that the device is in sleep mode. if a module current is listed, the current is for that specific module enabled and the device in sleep.
pic12f508/509/16f505 ds41236d-page 70 preliminary ? 2007 microchip technology inc. 10.2 dc characteristics: pic12f508/509/16f505 (extended) dc characteristics standard operating conditions (unless otherwise specified) operating temperature -40 c t a +125 c (extended) param no. sym. characteristic min. typ (1) max. units conditions d001 v dd supply voltage 2.0 5.5 v see figure 10-1 d002 v dr ram data retention voltage (2) ? 1.5* ? v device in sleep mode d003 v por v dd start voltage to ensure power-on reset ?vss? vsee section 7.4 "power-on reset (por)" for details d004 s vdd v dd rise rate to ensure power-on reset 0.05* ? ? v/ms see section 7.4 "power-on reset (por)" for details d010 i dd supply current (3,4) ? ? 175 0.625 275 1.1 a ma f osc = 4 mhz, v dd = 2.0v f osc = 4 mhz, v dd = 5.0v ? ? 500 1.5 650 2.2 a ma f osc = 10 mhz, v dd = 3.0v f osc = 20 mhz, v dd = 5.0v (pic16f515 only) ? ? 11 38 16 54 a a f osc = 32 khz, v dd = 2.0v f osc = 32 khz, v dd = 5.0v d020 i pd power-down current (5) ? ? 0.1 0.35 9.0 15.0 a a v dd = 2.0v v dd = 5.0v d022 i wdt wdt current (5) ? ? 1.0 7.0 18 22 a a v dd = 2.0v v dd = 5.0v * these parameters are characterized but not tested. note 1: data in the typical (?typ?) column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. 4: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. 5: for standby current measurements, the conditions are the same as idd, except that the device is in sleep mode. if a module current is listed, the current is for that specific module enabled and the device in sleep.
? 2007 microchip technology inc. preliminary ds41236d-page 71 pic12f508/509/16f505 table 10-1: dc characteristics: pic12f508/509/16f505 (industrial, extended) dc characteristics standard operating conditions (unless otherwise specified) operating temperature -40c t a +85c (industrial) -40c t a +125c (extended) operating voltage v dd range as described in dc specification param no. sym. characteristic min. typ? max. units conditions v il input low voltage i/o ports: d030 with ttl buffer vss ? 0.8v v for all 4.5 v dd 5.5v d030a vss ? 0.15 v dd v otherwise d031 with schmitt trigger buffer vss ? 0.15 v dd v d032 mclr , t0cki vss ? 0.15 v dd v d033 osc1 (in extrc) vss ? 0.15 v dd v (note1) d033 osc1 (in hs) vss ? 0.3 v dd v (note1) d033 osc1 (in xt and lp) vss ? 0.3 v (note1) v ih input high voltage i/o ports: ? d040 with ttl buffer 2.0 ? v dd v4.5 v dd 5.5v d040a 0.25 v dd + 0.8 ?v dd v otherwise d041 with schmitt trigger buffer 0.85 v dd ?v dd v for entire v dd range d042 mclr, t0cki 0.85 v dd ?v dd v d043 osc1 (in extrc) 0.85 v dd ?v dd v (note1) d043 osc1 (in hs) 0.7 v dd ?v dd v (note1) d043 osc1 (in xt and lp) 1.6 ? v dd v d070 i pur gpio/portb weak pull-up current (4) 50 250 400 av dd = 5v, v pin = v ss i il input leakage current (2), (3) d060 i/o ports ? ? 1 avss v pin v dd , pin at high-impedance d061 gp3/rb3/mclr i (5) 50 250 400 av dd = 5v d061a gp3/rb3/mclr i (6) ? 0.7 5 avss v pin v dd d063 osc1 ? ? 5 avss v pin v dd , xt, hs and lp oscillator configuratio output low voltage d080 i/o ports/clkout ? ? 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +85 c d080a ? ? 0.6 v i ol = 7.0 ma, v dd = 4.5v, -40 c to +125 c d083 osc2 ? ? 0.6 v i ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c d083a ? ? 0.6 v i ol = 1.2 ma, v dd = 4.5v, -40 c to +125 c output high voltage d090 i/o ports/clkout (3) v dd ? 0.7 ? ? v i oh = -3.0 ma, v dd = 4.5v, -40 c to +85 c d090a v dd ? 0.7 ? ? v i oh = -2.5 ma, v dd = 4.5v, -40 c to +125 c d092 osc2 v dd ? 0.7 ? ? v i oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c d092a v dd ? 0.7 ? ? v i oh = -1.0 ma, v dd = 4.5v, -40 c to +125 c capacitive loading specs on output pins d100 osc2 pin ? ? 15 pf in xt, hs and lp modes when external clock is used to drive osc1. d101 all i/o pins and osc2 ? ? 50 pf ? data in ?typ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in extrc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic12f508/509/ 16f505 be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as coming out of the pin. 4: does not include gp3/rb3. for gp3/rb3 see parameters d061 and d061a. 5: this specification applies to gp3/rb3/mclr configured as external mclr and gp3/rb3/mclr configured as input with internal pull-up enabled. 6: this specification applies when gp3/rb3/mclr is configured as an input with pull-up disabled. the leakage current of the mclr circuit is higher than the standard i/o logic.
pic12f508/509/16f505 ds41236d-page 72 preliminary ? 2007 microchip technology inc. table 10-2: pull-up resistor ranges ? pic12f508/509/16f505 v dd (volts) temperature ( c) min. typ. max. gp0(rbo)/gp1(rb1) 2.0 ?40 73k 105k 186k 25 73k 113k 187k 85 82k 123k 190k 125 86k 132k 190k 5.5 ?40 15k 21k 33k 25 15k 22k 34k 85 19k 26k 35k 125 23k 29k 35k gp3(rb3) 2.0 ?40 63k 81k 96k 25 77k 93k 116k 85 82k 96k 116k 125 86k 100k 119k 5.5 ?40 16k 20k 22k 25 16k 21k 23k 85 24k 25k 28k 125 26k 27k 29k * these parameters are characterized but not tested.
? 2007 microchip technology inc. preliminary ds41236d-page 73 pic12f508/509/16f505 10.3 timing parameter symbology and load conditions ? pic12f508/509/16f505 the timing parameter symbols have been created following one of the following formats: figure 10-3: load conditions ? pic12f508/509/16f505 figure 10-4: external clock timing ? pic12f508/509/16f505 1. tpps2pps 2. tpps t f frequency t time lowercase subscripts (pp) and their meanings: pp 2to mcmclr ck clkout osc oscillator cy cycle time os osc1 drt device reset timer t0 t0cki io i/o port wdt watchdog timer uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (high-impedance) v valid l low z high-impedance c l v ss pin legend: c l = 50 pf for all pins except osc2 15 pf for osc2 in xt, hs or lp modes when external clock is used to drive osc1 osc1 q4 q1 q2 q3 q4 q1 133 44 2
pic12f508/509/16f505 ds41236d-page 74 preliminary ? 2007 microchip technology inc. table 10-3: external clock timing requirements ? pic12f508/509/16f505 ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 c t a +85 c (industrial), -40 c t a +125 c (extended) operating voltage v dd range is described in section 10.1 "power- on reset (por)" param no. sym. characteristic min. typ (1) max. units conditions 1a f osc external clkin frequency (2) dc ? 4 mhz xt oscillator mode dc ? 20 mhz ec, hs oscillator mode (pic16f505 only) dc ? 200 khz lp oscillator mode oscillator frequency (2) ? ? 4 mhz extrc oscillator mode 0.1 ? 4 mhz xt oscillator mode 4 ? 20 mhz hs oscillator mode (pic16f505 only) ? ? 200 khz lp oscillator mode 1t osc external clkin period (2) 250 ? ? ns xt oscillator mode 50 ? ? ns ec, hs oscillator mode (pic16f505 only) 5? ? s lp oscillator mode oscillator period (2) 250 ? ? ns extrc oscillator mode 250 ? 10,000 ns xt oscillator mode 50 ? 250 ns hs oscillator mode (pic16f505 only) 5? ? s lp oscillator mode 2t cy instruction cycle time 200 4/f osc ?ns 3 tosl, to s h clock in (osc1) low or high time 50* ? ? ns xt oscillator 2* ? ? s lp oscillator 10* ? ? ns ec, hs oscillator (pic16f505 only) 4tosr, to s f clock in (osc1) rise or fall time ? ? 25* ns xt oscillator ? ? 50* ns lp oscillator ? ? 15* ns ec, hs oscillator (pic16f505 only) * these parameters are characterized but not tested. note 1: data in the typical (?typ?) column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the ?max? cycle time limit is ?dc? (no clock) for all devices.
? 2007 microchip technology inc. preliminary ds41236d-page 75 pic12f508/509/16f505 table 10-4: calibrated internal rc frequencies ? pic12f508/509/16f505 figure 10-5: i/o timing ? pic12f508/509/16f505 ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 c t a +85 c (industrial), -40 c t a +125 c (extended) param no. sym. characteristic freq tolerance min. typ? max. units conditions f10 f osc internal calibrated intosc frequency (1) 1% 3.96 4.00 4.04 mhz v dd = 3.5v, t a = 25 c 2% 3.92 4.00 4.08 mhz 2.5v v dd 5.5v 0 c t a +85 c 5% 3.80 4.00 4.20 mhz 2.0v v dd 5.5v -40 c t a +85 c (ind.) -40 c t a +125 c (ext.) * these parameters are characterized but not tested. ? data in the typical (?typ?) column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: to ensure these oscillator frequency tolerances, v dd and v ss must be capacitively decoupled as close to the device as possible. 0.1 uf and 0.01 uf values in parallel are recommended. osc1 i/o pin (input) i/o pin (output) q4 q1 q2 q3 17 20, 21 18 old value new value 19 note: all tests must be done with specified capacitive loads (see data sheet) 50 pf on i/o pins and clkout.
pic12f508/509/16f505 ds41236d-page 76 preliminary ? 2007 microchip technology inc. table 10-5: timing requirements ? pic12f508/509/16f505 figure 10-6: reset, watchdog timer and device reset timer timing ? pic12f508/509/16f505 ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 c t a +85 c (industrial) -40 c t a +125 c (extended) operating voltage v dd range is described in section 10.1 "power-on reset (por)" param no. sym. characteristic min. typ (1) max. units 17 t os h2 io vosc1 (q1 cycle) to port out valid (2), (3) ??100*ns 18 t os h2 io iosc1 (q2 cycle) to port input invalid (i/o in hold time) (2) 50 ? ? ns 19 t io v2 os h port input valid to osc1 (i/o in setup time) 20 ? ? ns 20 t io r port output rise time (3) ?1025**ns 21 t io f port output fall time (3) ?1025**ns * these parameters are characterized but not tested. ** these parameters are design targets and are not tested. note 1: data in the typical (?typ?) column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: measurements are taken in extrc mode. 3: see figure 10-3 for loading conditions. v dd mclr internal por drt timeout (2) internal reset watchdog timer reset 32 31 34 i/o pin (1) 32 32 34 30 note 1: i/o pins must be taken out of high-impedance mode by enabling the output drivers in software. 2: runs in mclr or wdt reset only in xt, lp and hs (pic16f505) modes.
? 2007 microchip technology inc. preliminary ds41236d-page 77 pic12f508/509/16f505 table 10-6: reset, watchdog timer and device reset timer ? pic12f508/509/16f505 ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 c t a +85 c (industrial) -40 c t a +125 c (extended) param no. sym. characteristic min. typ (1) max. units conditions 30 t mc lmclr pulse width (low) 2000* ? ? ns v dd = 5.0v 31 t wdt watchdog timer time-out period (no prescaler) 9* 9* 18* 18* 30* 40* ms ms v dd = 5.0v (industrial) v dd = 5.0v (extended) 32 t drt device reset timer period (2) 9* 9* 18* 18* 30* 40* ms ms v dd = 5.0v (industrial) v dd = 5.0v (extended) 34 t ioz i/o high-impedance from mclr low ? ? 2000* ns * these parameters are characterized but not tested. note 1: data in the typical (?typ?) column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested.
pic12f508/509/16f505 ds41236d-page 78 preliminary ? 2007 microchip technology inc. figure 10-7: timer0 clock timings ? pic12f508/509/16f505 table 10-7: timer0 clock requirements ? pic12f508/509/16f505 ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 c t a +85 c (industrial) -40 c t a +125 c (extended) operating voltage v dd range is described in section 10.1 "power-on reset (por)" param no. sym. characteristic min. typ (1) max. units conditions 40 tt0h t0cki high pulse width no prescaler 0.5 t cy + 20* ? ? ns with prescaler 10* ? ? ns 41 tt0l t0cki low pulse width no prescaler 0.5 t cy + 20* ? ? ns with prescaler 10* ? ? ns 42 tt0p t0cki period 20 or t cy + 40* n ? ? ns whichever is greater. n = prescale value (1, 2, 4,..., 256) * these parameters are characterized but not tested. note 1: data in the typical (?typ?) column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. t0cki 40 41 42
? 2007 microchip technology inc. preliminary ds41236d-page 79 pic12f508/509/16f505 11.0 dc and ac characteristics graphs and charts ?typical? represents the mean of the distribution at 25 c. ?maximum? or ?minimum? represents (mean + 3 ) or (mean - 3 ) respectively, where s is a standard deviation, over each temperature range. figure 11-1: i dd vs. v dd at f osc = 4 mhz note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. 0 200 400 600 800 1,000 1,200 1,400 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i dd ( a) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) 4 mhz 4 mhz maximum typical
pic12f508/509/16f505 ds41236d-page 80 preliminary ? 2007 microchip technology inc. figure 11-2: i dd vs . f osc over v dd (hs m ode , pic16f505 only ) figure 11-3: typical i pd vs. v dd (sleep mode, all peripherals disabled) 3.00 2.50 2.00 1.50 1.00 0.50 0.00 5 10 15 20 25 max. 5v typical 5v max. 3v typical 3v fosc (mhz) i dd (ma) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) typical (sleep mode all peripherals disabled) 0.0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( a) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c)
? 2007 microchip technology inc. preliminary ds41236d-page 81 pic12f508/509/16f505 figure 11-4: maximum i pd vs. v dd (sleep mode, all peripherals disabled) figure 11-5: typical wdt i pd vs. v dd maximum (sleep mode all peripherals disabled) max. 125c max. 85c 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( a) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) 0 1 2 3 4 5 6 7 8 9 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( a) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c)
pic12f508/509/16f505 ds41236d-page 82 preliminary ? 2007 microchip technology inc. figure 11-6: maximum wdt i pd vs. v dd over temperature figure 11-7: wdt time-out or device reset timer vs. v dd over temperature (no wdt prescaler) (1) m ax i mum max. 125c max. 85c 0.0 5.0 10.0 15.0 20.0 25.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( a) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) 0 5 10 15 20 25 30 35 40 45 50 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) time (ms) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) max. 125c max. 85c typical. 25c min. -40c note 1: device reset timer (drt) values are for case of reset of power-up. table 7-6 shows drt values for the case of other types of reset events.
? 2007 microchip technology inc. preliminary ds41236d-page 83 pic12f508/509/16f505 figure 11-8: v ol vs. i ol over temperature (v dd = 3.0v) figure 11-9: v ol vs. i ol over temperature (v dd = 5.0v) (vdd = 3v , - 40 c to 125 c) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 i ol (ma) v ol (v) max. 85c max. 125c typical 25c min. -40c typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 i ol (ma) v ol (v) typical: statistical mean @25c maximum: meas + 3 (-40c to 125c) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) max. 85c typ. 25c min. -40c max. 125c
pic12f508/509/16f505 ds41236d-page 84 preliminary ? 2007 microchip technology inc. figure 11-10: v oh vs. i oh over temperature (v dd = 3.0v) figure 11-11: v oh vs. i oh over temperature (v dd = 5.0v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 i oh (ma) v oh (v) typ. 25c max. -40c min. 125c typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) (, ) 3.0 3.5 4.0 4.5 5.0 5.5 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 i oh (ma) v oh (v) max. -40c typ. 25c min. 125c typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c)
? 2007 microchip technology inc. preliminary ds41236d-page 85 pic12f508/509/16f505 figure 11-12: ttl input threshold v in vs. v dd figure 11-13: schmitt trigger input threshold v in vs. v dd (ttl input, -40c to 125c) 0.5 0.7 0.9 1.1 1.3 1.5 1.7 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) v in (v) typ. 25c max. -40c min. 125c typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) (st i npu t , - 40 c to 125 c) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) v in (v) v ih max. 125c v ih min. -40c v il min. 125c v il max. -40c typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c)
pic12f508/509/16f505 ds41236d-page 86 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds41236d-page 87 pic12f508/509/16f505 12.0 packaging information 12.1 package marking information xxxxxnnn 8-lead pdip xxxxxxxx yyww /p 017 example 12f508-i 0410 8-lead soic (3.90 mm) xxxxxxxx xxxxyyww nnn example 12f509-i /sn 0410 017 8-lead msop xxxxxx ywwnnn example 12f509 0431017 3 e 3 e x x x y w w n n 8-lead 2x3 dfn* b e 0 6 1 0 1 7 example note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard pic ? device marking consists of microchip part number, year code, week code, and traceability code. for pic device marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. 3 e 3 e
pic12f508/509/16f505 ds41236d-page 88 preliminary ? 2007 microchip technology inc. 12.1 package marking information (continued) xxxxxxxxxxxxxx xxxxxxxxxxxxxx yywwnnn 14-lead pdip (300 mil) 14-lead soic (3.90 mm) xxxxxxxxxxx yywwnnn example pic16f505-e 0431017 xxxxxxxxxxx 14-lead tssop (4.4 mm) xxxxxxxx yyww example 16f505-i 0431 nnn 017 /sl0125 example pic16f505 0410017 0215 3 e -i/p table 12-1: 8-lead 2x3 dfn (mc) top marking part number marking pic12f508 (t) - i/mc bn0 pic12f508-e/mc bp0 pic12f509 (t) - i/mc bq0 pic12f509-e/mc br0
? 2007 microchip technology inc. preliminary ds41236d-page 89 pic12f508/509/16f505

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? 2007 microchip technology inc. preliminary ds41236d-page 97 pic12f508/509/16f505 appendix a: revision history revision a (april 2004) original data sheet for pic12f508/509/16f505 devices revision b (june 2005) update packages revision c (03/2007) revised table 3-2 legend; revised table 3-3 rb3 and legend; revised table 10-4 f10; replaced package drawings (rev. an); added dfn package; replaced development support section; revised product id system. revision d (12/2007) revised title; operating current; table 1-1 added dfn and revised note; revised section 3.0, last paragraph; revised figure 4-4; revised table 4-2 (fsr); revised register 7-1 and register 7-2; revised section 7.2.2; revised table 7-3, note 2; revised table 7-4 (fsr) and note 2; deleted section 7.3.1: external clock in and figure 7-6; revised new section 7.3.1; replaced tbd with new data in tables 10-4 and 10-5; revised tables 10-1 (industrial), 10-2 (extended), and tables 10-1 (industrial, extended) and 10-2 (pull-up resistor ranges), 10-3, 10-4 and 10-6; revised figure 10-1, figure 10-2; section 11.0, added char data; revised package marking information; revised product id system.
pic12f508/509/16f505 ds41236d-page 98 preliminary ? 2007 microchip technology inc. notes:
2007 microchip technology inc. preliminary ds41236d-page 99 pic12f508/509/16f505 index a alu ....................................................................................... 9 assembler mpasm assembler..................................................... 64 b block diagram on-chip reset circuit ................................................. 48 timer0......................................................................... 33 tmr0/wdt prescaler................................................. 37 watchdog timer.......................................................... 51 brown-out protection circuit .............................................. 52 c c compilers mplab c18 ................................................................ 64 mplab c30 ................................................................ 64 carry ..................................................................................... 9 clocking scheme ................................................................ 14 code protection ............................................................ 39, 53 configuration bits................................................................ 39 configuration word ............................................................. 41 customer change notification service ............................. 101 customer notification service........................................... 101 customer support............................................................. 101 d dc and ac characteristics ................................................. 79 development support ......................................................... 63 digit carry ............................................................................. 9 e errata .................................................................................... 3 f family of devices pic12f508/509/pic16f505.......................................... 5 fsr ..................................................................................... 26 i i/o interfacing ..................................................................... 29 i/o ports .............................................................................. 29 i/o programming considerations........................................ 31 id locations .................................................................. 39, 53 indf.................................................................................... 26 indirect data addressing..................................................... 26 instruction cycle ................................................................. 14 instruction flow/pipelining .................................................. 14 instruction set summary..................................................... 56 internet address................................................................ 101 l loading of pc ..................................................................... 25 m memory organization.......................................................... 15 data memory .............................................................. 16 program memory (pic12f508/509)............................ 15 program memory (pic16f505)................................... 16 microchip internet web site .............................................. 101 mplab asm30 assembler, linker, librarian ..................... 64 mplab icd 2 in-circuit debugger ..................................... 65 mplab ice 2000 high-performance universal in-circuit emulator ...................................................... 65 mplab integrated development environment software.... 63 mplab pm3 device programmer ...................................... 65 mplab real ice in-circuit emulator system .................. 65 mplink object linker/mplib object librarian .................. 64 o option register................................................................... 22 osc selection..................................................................... 39 osccal register............................................................... 24 oscillator configurations..................................................... 42 oscillator types hs............................................................................... 42 lp ............................................................................... 42 rc .............................................................................. 42 xt ............................................................................... 42 p pic12f508/509/16f505 device varieties ............................ 7 picstart plus development programmer....................... 66 por device reset timer (drt) ................................... 39, 50 pd ............................................................................... 52 power-on reset (por)............................................... 39 to ............................................................................... 52 portb ............................................................................... 29 power-down mode.............................................................. 53 prescaler ............................................................................ 36 program counter ................................................................ 25 q q cycles .............................................................................. 14 r rc oscillator....................................................................... 43 reader response............................................................. 102 read-modify-write.............................................................. 31 register file map pic12f508 ................................................................. 17 pic12f509 ................................................................. 17 pic16f505 ................................................................. 17 registers special function ......................................................... 18 reset .................................................................................. 39 reset on brown-out ........................................................... 52 s sleep ............................................................................ 39, 53 software simulator (mplab sim) ...................................... 64 special features of the cpu .............................................. 39 special function registers ................................................. 18 stack................................................................................... 25 status register ............................................................... 9, 20 t timer0 timer0 ........................................................................ 33 timer0 (tmr0) module .............................................. 33 tmr0 with external clock .......................................... 35 timing diagrams and specifications .................................. 73 timing parameter symbology and load conditions .......... 73 tris registers ................................................................... 29
pic12f508/509/16f505 ds41236d-page 100 preliminary ? 2007 microchip technology inc. w wake-up from sleep ........................................................... 53 watchdog timer (wdt) ................................................ 39, 50 period.......................................................................... 50 programming considerations ..................................... 50 www address.................................................................. 101 www, on-line support........................................................ 3 z zero bit .................................................................................. 9
? 2007 microchip technology inc. preliminary ds41236d-page 101 pic12f508/509/16f505 the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com
pic12f508/509/16f505 ds41236d-page 102 preliminary ? 2007 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds41236d pic12f508/509/16f505 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2007 microchip technology inc. preliminary ds41236d-page 103 pic12f508/509/16f505 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device: pic16f505 pic12f508 pic12f509 pic16f505t (1) pic12f508t (2) pic12f509t (2) temperature range: i= -40 c to +85 c (industrial) e= -40 c to +125 c (extended) package: mc = 8l dfn 2x3 (dual flatpack no-leads) (3, 4) ms = micro-small outline package (msop) (3, 4) p = plastic (pdip) (4) sl = 14l small outline, 3.90 mm (soic) (4) sn = 8l small outline, 3.90 mm narrow (soic) (4) st = thin shrink small outline (tssop) (4) pattern: special requirements examples: a) pic12f508-e/p 301 = extended temp., pdip package, qtp pattern #301 b) pic12f508-i/sn = industrial temp., soic package c) pic12f508t-e/p = extended temp., pdip package, tape and reel note 1: t = in tape and reel soic and tssop packages only 2: t = in tape and reel soic and msop packages only. 3: pic12f508/pic12f509 only. 4: pb-free. note: tape and reel available for only the following packages: soic, msop and tssop.
ds41236d-page 104 preliminary ? 2007 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - fuzhou tel: 86-591-8750-3506 fax: 86-591-8750-3521 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - shunde tel: 86-757-2839-5507 fax: 86-757-2839-5571 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 asia/pacific india - bangalore tel: 91-80-4182-8400 fax: 91-80-4182-8422 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-572-9526 fax: 886-3-572-6459 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 10/05/07

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